1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/dma/arm-pl08x.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ARM PrimeCells PL080 and PL081 and derivatives DMA controller
10 - Vinod Koul <vkoul@kernel.org>
13 - $ref: /schemas/arm/primecell.yaml#
14 - $ref: dma-controller.yaml#
16 # We need a select here so we don't match all nodes with 'arm,primecell'
34 - const: arm,primecell
36 - const: faraday,ftdma020
38 - const: arm,primecell
42 description: Address range of the PL08x registers
46 description: The PL08x interrupt number
50 description: The clock running the IP core clock
55 lli-bus-interface-ahb1:
57 description: if AHB master 1 is eligible for fetching LLIs
59 lli-bus-interface-ahb2:
61 description: if AHB master 2 is eligible for fetching LLIs
63 mem-bus-interface-ahb1:
65 description: if AHB master 1 is eligible for fetching memory contents
67 mem-bus-interface-ahb2:
69 description: if AHB master 2 is eligible for fetching memory contents
72 $ref: /schemas/types.yaml#/definitions/uint32
82 description: the size of the bursts for memcpy
85 $ref: /schemas/types.yaml#/definitions/uint32
91 description: bus width used for memcpy in bits. FTDMAC020 also accept 64 bits
103 unevaluatedProperties: false
107 dmac0: dma-controller@10130000 {
108 compatible = "arm,pl080", "arm,primecell";
109 reg = <0x10130000 0x1000>;
110 interrupt-parent = <&vica>;
112 clocks = <&hclkdma0>;
113 clock-names = "apb_pclk";
114 lli-bus-interface-ahb1;
115 lli-bus-interface-ahb2;
116 mem-bus-interface-ahb2;
117 memcpy-burst-size = <256>;
118 memcpy-bus-width = <32>;
122 #include <dt-bindings/interrupt-controller/irq.h>
123 #include <dt-bindings/reset/cortina,gemini-reset.h>
124 #include <dt-bindings/clock/cortina,gemini-clock.h>
125 dma-controller@67000000 {
126 compatible = "faraday,ftdma020", "arm,pl080", "arm,primecell";
127 /* Faraday Technology FTDMAC020 variant */
128 arm,primecell-periphid = <0x0003b080>;
129 reg = <0x67000000 0x1000>;
130 interrupts = <9 IRQ_TYPE_EDGE_RISING>;
131 resets = <&syscon GEMINI_RESET_DMAC>;
132 clocks = <&syscon GEMINI_CLK_AHB>;
133 clock-names = "apb_pclk";
134 /* Bus interface AHB1 (AHB0) is totally tilted */
135 lli-bus-interface-ahb2;
136 mem-bus-interface-ahb2;
137 memcpy-burst-size = <256>;
138 memcpy-bus-width = <32>;