1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2 # Copyright 2019 Texas Instruments Incorporated
5 $id: http://devicetree.org/schemas/display/ti/ti,j721e-dss.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Texas Instruments J721E Display Subsystem
11 - Jyri Sarha <jsarha@ti.com>
12 - Tomi Valkeinen <tomi.valkeinen@ti.com>
15 The J721E TI Keystone Display SubSystem with four output ports and
16 four video planes. There is two full video planes and two "lite
17 planes" without scaling support. The video ports can be connected to
18 the SoC's DPI pins or to integrated display bridges on the SoC.
26 - description: common_m DSS Master common
27 - description: common_s0 DSS Shared common 0
28 - description: common_s1 DSS Shared common 1
29 - description: common_s2 DSS Shared common 2
30 - description: VIDL1 light video plane 1
31 - description: VIDL2 light video plane 2
32 - description: VID1 video plane 1
33 - description: VID1 video plane 2
34 - description: OVR1 overlay manager for vp1
35 - description: OVR2 overlay manager for vp2
36 - description: OVR3 overlay manager for vp3
37 - description: OVR4 overlay manager for vp4
38 - description: VP1 video port 1
39 - description: VP2 video port 2
40 - description: VP3 video port 3
41 - description: VP4 video port 4
42 - description: WB Write Back
66 - description: fck DSS functional clock
67 - description: vp1 Video Port 1 pixel clock
68 - description: vp2 Video Port 2 pixel clock
69 - description: vp3 Video Port 3 pixel clock
70 - description: vp4 Video Port 4 pixel clock
84 assigned-clock-parents:
90 - description: common_m DSS Master common
91 - description: common_s0 DSS Shared common 0
92 - description: common_s1 DSS Shared common 1
93 - description: common_s2 DSS Shared common 2
104 description: phandle to the associated power domain
110 $ref: /schemas/graph.yaml#/properties/ports
114 $ref: /schemas/graph.yaml#/properties/port
116 The output port node form video port 1
119 $ref: /schemas/graph.yaml#/properties/port
121 The output port node from video port 2
124 $ref: /schemas/graph.yaml#/properties/port
126 The output port node from video port 3
129 $ref: /schemas/graph.yaml#/properties/port
131 The output port node from video port 4
133 max-memory-bandwidth:
134 $ref: /schemas/types.yaml#/definitions/uint32
136 Input memory (from main memory to dispc) bandwidth limit in
149 additionalProperties: false
153 #include <dt-bindings/interrupt-controller/arm-gic.h>
154 #include <dt-bindings/interrupt-controller/irq.h>
155 #include <dt-bindings/soc/ti,sci_pm_domain.h>
158 compatible = "ti,j721e-dss";
159 reg = <0x04a00000 0x10000>, /* common_m */
160 <0x04a10000 0x10000>, /* common_s0*/
161 <0x04b00000 0x10000>, /* common_s1*/
162 <0x04b10000 0x10000>, /* common_s2*/
163 <0x04a20000 0x10000>, /* vidl1 */
164 <0x04a30000 0x10000>, /* vidl2 */
165 <0x04a50000 0x10000>, /* vid1 */
166 <0x04a60000 0x10000>, /* vid2 */
167 <0x04a70000 0x10000>, /* ovr1 */
168 <0x04a90000 0x10000>, /* ovr2 */
169 <0x04ab0000 0x10000>, /* ovr3 */
170 <0x04ad0000 0x10000>, /* ovr4 */
171 <0x04a80000 0x10000>, /* vp1 */
172 <0x04aa0000 0x10000>, /* vp2 */
173 <0x04ac0000 0x10000>, /* vp3 */
174 <0x04ae0000 0x10000>, /* vp4 */
175 <0x04af0000 0x10000>; /* wb */
176 reg-names = "common_m", "common_s0",
177 "common_s1", "common_s2",
178 "vidl1", "vidl2","vid1","vid2",
179 "ovr1", "ovr2", "ovr3", "ovr4",
180 "vp1", "vp2", "vp3", "vp4",
182 clocks = <&k3_clks 152 0>,
187 clock-names = "fck", "vp1", "vp2", "vp3", "vp4";
188 power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>;
189 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>,
190 <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>,
191 <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>,
192 <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
193 interrupt-names = "common_m",
198 #address-cells = <1>;
203 dpi_out_0: endpoint {
204 remote-endpoint = <&dp_bridge_input>;