1 # SPDX-License-Identifier: GPL-2.0
4 $id: http://devicetree.org/schemas/display/rockchip/rockchip-vop.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Rockchip SoC display controller (VOP)
10 VOP (Video Output Processor) is the display controller for the Rockchip
11 series of SoCs which transfers the image data from a video memory
12 buffer to an external LCD interface.
15 - Sandy Huang <hjc@rock-chips.com>
16 - Heiko Stuebner <heiko@sntech.de>
21 - rockchip,px30-vop-big
22 - rockchip,px30-vop-lit
32 - rockchip,rk3399-vop-big
33 - rockchip,rk3399-vop-lit
40 Must contain one entry corresponding to the base address and length
41 of the register space.
43 Can optionally contain a second entry corresponding to
44 the CRTC gamma LUT address.
49 The VOP interrupt is shared by several interrupt sources, such as
50 frame start (VSYNC), line flag and other status interrupts.
54 - description: Clock for ddr buffer transfer.
55 - description: Pixel clock.
56 - description: Clock for the ahb bus to R/W the phy regs.
74 $ref: /schemas/graph.yaml#/properties/port
98 additionalProperties: false
102 #include <dt-bindings/clock/rk3288-cru.h>
103 #include <dt-bindings/interrupt-controller/arm-gic.h>
104 #include <dt-bindings/power/rk3288-power.h>
105 vopb: vopb@ff930000 {
106 compatible = "rockchip,rk3288-vop";
107 reg = <0xff930000 0x19c>,
109 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
110 clocks = <&cru ACLK_VOP0>,
113 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
114 power-domains = <&power RK3288_PD_VIO>;
115 resets = <&cru SRST_LCDC1_AXI>,
116 <&cru SRST_LCDC1_AHB>,
117 <&cru SRST_LCDC1_DCLK>;
118 reset-names = "axi", "ahb", "dclk";
119 iommus = <&vopb_mmu>;
121 #address-cells = <1>;
123 vopb_out_edp: endpoint@0 {
125 remote-endpoint = <&edp_in_vopb>;
127 vopb_out_hdmi: endpoint@1 {
129 remote-endpoint = <&hdmi_in_vopb>;