1 # SPDX-License-Identifier: GPL-2.0
4 $id: http://devicetree.org/schemas/display/rockchip/rockchip,dw-mipi-dsi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Rockchip specific extensions to the Synopsys Designware MIPI DSI
10 - Sandy Huang <hjc@rock-chips.com>
11 - Heiko Stuebner <heiko@sntech.de>
17 - rockchip,px30-mipi-dsi
18 - rockchip,rk3288-mipi-dsi
19 - rockchip,rk3399-mipi-dsi
20 - rockchip,rk3568-mipi-dsi
21 - rockchip,rv1126-mipi-dsi
22 - const: snps,dw-mipi-dsi
42 $ref: /schemas/types.yaml#/definitions/phandle
44 This SoC uses GRF regs to switch between vopl/vopb.
55 Defined when in use as ISP phy.
73 - $ref: /schemas/display/bridge/snps,dw-mipi-dsi.yaml#
79 - rockchip,px30-mipi-dsi
80 - rockchip,rk3568-mipi-dsi
81 - rockchip,rv1126-mipi-dsi
99 const: rockchip,rk3288-mipi-dsi
113 const: rockchip,rk3399-mipi-dsi
123 unevaluatedProperties: false
127 #include <dt-bindings/clock/rk3288-cru.h>
128 #include <dt-bindings/interrupt-controller/arm-gic.h>
129 #include <dt-bindings/interrupt-controller/irq.h>
131 mipi_dsi: dsi@ff960000 {
132 compatible = "rockchip,rk3288-mipi-dsi", "snps,dw-mipi-dsi";
133 reg = <0xff960000 0x4000>;
134 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
135 clocks = <&cru SCLK_MIPIDSI_24M>, <&cru PCLK_MIPI_DSI0>;
136 clock-names = "ref", "pclk";
137 resets = <&cru SRST_MIPIDSI0>;
139 rockchip,grf = <&grf>;
142 #address-cells = <1>;
147 #address-cells = <1>;
150 mipi_in_vopb: endpoint@0 {
152 remote-endpoint = <&vopb_out_mipi>;
154 mipi_in_vopl: endpoint@1 {
156 remote-endpoint = <&vopl_out_mipi>;
163 mipi_out_panel: endpoint {
164 remote-endpoint = <&panel_in_mipi>;