1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
4 $id: http://devicetree.org/schemas/display/msm/qcom,sm8650-dpu.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm SM8650 Display DPU
10 - Neil Armstrong <neil.armstrong@linaro.org>
12 $ref: /schemas/display/msm/dpu-common.yaml#
16 const: qcom,sm8650-dpu
20 - description: Address offset and size for mdp register set
21 - description: Address offset and size for vbif register set
30 - description: Display hf axi
31 - description: Display MDSS ahb
32 - description: Display lut
33 - description: Display core
34 - description: Display vsync
51 unevaluatedProperties: false
55 #include <dt-bindings/interrupt-controller/arm-gic.h>
56 #include <dt-bindings/power/qcom,rpmhpd.h>
58 display-controller@ae01000 {
59 compatible = "qcom,sm8650-dpu";
60 reg = <0x0ae01000 0x8f000>,
62 reg-names = "mdp", "vbif";
64 clocks = <&gcc_axi_clk>,
66 <&dispcc_mdp_lut_clk>,
69 clock-names = "nrt_bus",
75 assigned-clocks = <&dispcc_vsync_clk>;
76 assigned-clock-rates = <19200000>;
78 operating-points-v2 = <&mdp_opp_table>;
79 power-domains = <&rpmhpd RPMHPD_MMCX>;
81 interrupt-parent = <&mdss>;
90 dpu_intf1_out: endpoint {
91 remote-endpoint = <&dsi0_in>;
97 dpu_intf2_out: endpoint {
98 remote-endpoint = <&dsi1_in>;
103 mdp_opp_table: opp-table {
104 compatible = "operating-points-v2";
107 opp-hz = /bits/ 64 <200000000>;
108 required-opps = <&rpmhpd_opp_low_svs>;
112 opp-hz = /bits/ 64 <325000000>;
113 required-opps = <&rpmhpd_opp_svs>;
117 opp-hz = /bits/ 64 <375000000>;
118 required-opps = <&rpmhpd_opp_svs_l1>;
122 opp-hz = /bits/ 64 <514000000>;
123 required-opps = <&rpmhpd_opp_nom>;