1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
4 $id: http://devicetree.org/schemas/display/msm/qcom,sm8550-mdss.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm SM8550 Display MDSS
10 - Neil Armstrong <neil.armstrong@linaro.org>
13 SM8550 MSM Mobile Display Subsystem(MDSS), which encapsulates sub-blocks like
14 DPU display controller, DSI and DP interfaces etc.
16 $ref: /schemas/display/msm/mdss-common.yaml#
20 const: qcom,sm8550-mdss
24 - description: Display MDSS AHB
25 - description: Display AHB
26 - description: Display hf AXI
27 - description: Display core
39 "^display-controller@[0-9a-f]+$":
41 additionalProperties: true
45 const: qcom,sm8550-dpu
47 "^displayport-controller@[0-9a-f]+$":
49 additionalProperties: true
54 - const: qcom,sm8550-dp
55 - const: qcom,sm8350-dp
59 additionalProperties: true
64 - const: qcom,sm8550-dsi-ctrl
65 - const: qcom,mdss-dsi-ctrl
69 additionalProperties: true
73 const: qcom,sm8550-dsi-phy-4nm
78 unevaluatedProperties: false
82 #include <dt-bindings/clock/qcom,sm8550-dispcc.h>
83 #include <dt-bindings/clock/qcom,sm8550-gcc.h>
84 #include <dt-bindings/clock/qcom,rpmh.h>
85 #include <dt-bindings/interrupt-controller/arm-gic.h>
86 #include <dt-bindings/interconnect/qcom,sm8550-rpmh.h>
87 #include <dt-bindings/power/qcom,rpmhpd.h>
89 display-subsystem@ae00000 {
90 compatible = "qcom,sm8550-mdss";
91 reg = <0x0ae00000 0x1000>;
94 interconnects = <&mmss_noc MASTER_MDP 0 &gem_noc SLAVE_LLCC 0>,
95 <&mc_virt MASTER_LLCC 0 &mc_virt SLAVE_EBI1 0>;
96 interconnect-names = "mdp0-mem", "mdp1-mem";
98 resets = <&dispcc DISP_CC_MDSS_CORE_BCR>;
100 power-domains = <&dispcc MDSS_GDSC>;
102 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
103 <&gcc GCC_DISP_AHB_CLK>,
104 <&gcc GCC_DISP_HF_AXI_CLK>,
105 <&dispcc DISP_CC_MDSS_MDP_CLK>;
106 clock-names = "iface", "bus", "nrt_bus", "core";
108 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
109 interrupt-controller;
110 #interrupt-cells = <1>;
112 iommus = <&apps_smmu 0x1c00 0x2>;
114 #address-cells = <1>;
118 display-controller@ae01000 {
119 compatible = "qcom,sm8550-dpu";
120 reg = <0x0ae01000 0x8f000>,
122 reg-names = "mdp", "vbif";
124 clocks = <&gcc GCC_DISP_AHB_CLK>,
125 <&gcc GCC_DISP_HF_AXI_CLK>,
126 <&dispcc DISP_CC_MDSS_AHB_CLK>,
127 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
128 <&dispcc DISP_CC_MDSS_MDP_CLK>,
129 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
137 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
138 assigned-clock-rates = <19200000>;
140 operating-points-v2 = <&mdp_opp_table>;
141 power-domains = <&rpmhpd RPMHPD_MMCX>;
143 interrupt-parent = <&mdss>;
147 #address-cells = <1>;
152 dpu_intf1_out: endpoint {
153 remote-endpoint = <&dsi0_in>;
159 dpu_intf2_out: endpoint {
160 remote-endpoint = <&dsi1_in>;
165 mdp_opp_table: opp-table {
166 compatible = "operating-points-v2";
169 opp-hz = /bits/ 64 <200000000>;
170 required-opps = <&rpmhpd_opp_low_svs>;
174 opp-hz = /bits/ 64 <325000000>;
175 required-opps = <&rpmhpd_opp_svs>;
179 opp-hz = /bits/ 64 <375000000>;
180 required-opps = <&rpmhpd_opp_svs_l1>;
184 opp-hz = /bits/ 64 <514000000>;
185 required-opps = <&rpmhpd_opp_nom>;
191 compatible = "qcom,sm8550-dsi-ctrl", "qcom,mdss-dsi-ctrl";
192 reg = <0x0ae94000 0x400>;
193 reg-names = "dsi_ctrl";
195 interrupt-parent = <&mdss>;
198 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
199 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
200 <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
201 <&dispcc DISP_CC_MDSS_ESC0_CLK>,
202 <&dispcc DISP_CC_MDSS_AHB_CLK>,
203 <&gcc GCC_DISP_HF_AXI_CLK>;
204 clock-names = "byte",
211 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
212 <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
213 assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>;
215 operating-points-v2 = <&dsi_opp_table>;
216 power-domains = <&rpmhpd RPMHPD_MMCX>;
221 #address-cells = <1>;
225 #address-cells = <1>;
231 remote-endpoint = <&dpu_intf1_out>;
242 dsi_opp_table: opp-table {
243 compatible = "operating-points-v2";
246 opp-hz = /bits/ 64 <187500000>;
247 required-opps = <&rpmhpd_opp_low_svs>;
251 opp-hz = /bits/ 64 <300000000>;
252 required-opps = <&rpmhpd_opp_svs>;
256 opp-hz = /bits/ 64 <358000000>;
257 required-opps = <&rpmhpd_opp_svs_l1>;
262 dsi0_phy: phy@ae94400 {
263 compatible = "qcom,sm8550-dsi-phy-4nm";
264 reg = <0x0ae95000 0x200>,
267 reg-names = "dsi_phy",
274 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
275 <&rpmhcc RPMH_CXO_CLK>;
276 clock-names = "iface", "ref";
280 compatible = "qcom,sm8550-dsi-ctrl", "qcom,mdss-dsi-ctrl";
281 reg = <0x0ae96000 0x400>;
282 reg-names = "dsi_ctrl";
284 interrupt-parent = <&mdss>;
287 clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>,
288 <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>,
289 <&dispcc DISP_CC_MDSS_PCLK1_CLK>,
290 <&dispcc DISP_CC_MDSS_ESC1_CLK>,
291 <&dispcc DISP_CC_MDSS_AHB_CLK>,
292 <&gcc GCC_DISP_HF_AXI_CLK>;
293 clock-names = "byte",
300 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>,
301 <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>;
302 assigned-clock-parents = <&dsi1_phy 0>, <&dsi1_phy 1>;
304 operating-points-v2 = <&dsi_opp_table>;
305 power-domains = <&rpmhpd RPMHPD_MMCX>;
310 #address-cells = <1>;
314 #address-cells = <1>;
320 remote-endpoint = <&dpu_intf2_out>;
332 dsi1_phy: phy@ae96400 {
333 compatible = "qcom,sm8550-dsi-phy-4nm";
334 reg = <0x0ae97000 0x200>,
337 reg-names = "dsi_phy",
344 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
345 <&rpmhcc RPMH_CXO_CLK>;
346 clock-names = "iface", "ref";