1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
4 $id: http://devicetree.org/schemas/display/msm/qcom,sm8550-dpu.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm SM8550 Display DPU
10 - Neil Armstrong <neil.armstrong@linaro.org>
12 $ref: /schemas/display/msm/dpu-common.yaml#
16 const: qcom,sm8550-dpu
20 - description: Address offset and size for mdp register set
21 - description: Address offset and size for vbif register set
30 - description: Display AHB
31 - description: Display hf axi
32 - description: Display MDSS ahb
33 - description: Display lut
34 - description: Display core
35 - description: Display vsync
53 unevaluatedProperties: false
57 #include <dt-bindings/clock/qcom,sm8550-dispcc.h>
58 #include <dt-bindings/clock/qcom,sm8550-gcc.h>
59 #include <dt-bindings/interrupt-controller/arm-gic.h>
60 #include <dt-bindings/power/qcom,rpmhpd.h>
62 display-controller@ae01000 {
63 compatible = "qcom,sm8550-dpu";
64 reg = <0x0ae01000 0x8f000>,
66 reg-names = "mdp", "vbif";
68 clocks = <&gcc GCC_DISP_AHB_CLK>,
69 <&gcc GCC_DISP_HF_AXI_CLK>,
70 <&dispcc DISP_CC_MDSS_AHB_CLK>,
71 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
72 <&dispcc DISP_CC_MDSS_MDP_CLK>,
73 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
81 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
82 assigned-clock-rates = <19200000>;
84 operating-points-v2 = <&mdp_opp_table>;
85 power-domains = <&rpmhpd RPMHPD_MMCX>;
87 interrupt-parent = <&mdss>;
96 dpu_intf1_out: endpoint {
97 remote-endpoint = <&dsi0_in>;
103 dpu_intf2_out: endpoint {
104 remote-endpoint = <&dsi1_in>;
109 mdp_opp_table: opp-table {
110 compatible = "operating-points-v2";
113 opp-hz = /bits/ 64 <200000000>;
114 required-opps = <&rpmhpd_opp_low_svs>;
118 opp-hz = /bits/ 64 <325000000>;
119 required-opps = <&rpmhpd_opp_svs>;
123 opp-hz = /bits/ 64 <375000000>;
124 required-opps = <&rpmhpd_opp_svs_l1>;
128 opp-hz = /bits/ 64 <514000000>;
129 required-opps = <&rpmhpd_opp_nom>;