1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
4 $id: http://devicetree.org/schemas/display/msm/qcom,sm8450-mdss.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm SM8450 Display MDSS
10 - Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
13 SM8450 MSM Mobile Display Subsystem(MDSS), which encapsulates sub-blocks like
14 DPU display controller, DSI and DP interfaces etc.
16 $ref: /schemas/display/msm/mdss-common.yaml#
20 const: qcom,sm8450-mdss
24 - description: Display AHB
25 - description: Display hf AXI
26 - description: Display sf AXI
27 - description: Display core
39 "^display-controller@[0-9a-f]+$":
41 additionalProperties: true
45 const: qcom,sm8450-dpu
47 "^displayport-controller@[0-9a-f]+$":
49 additionalProperties: true
54 - const: qcom,sm8450-dp
55 - const: qcom,sm8350-dp
59 additionalProperties: true
64 - const: qcom,sm8450-dsi-ctrl
65 - const: qcom,mdss-dsi-ctrl
69 additionalProperties: true
73 const: qcom,sm8450-dsi-phy-5nm
78 unevaluatedProperties: false
82 #include <dt-bindings/clock/qcom,sm8450-dispcc.h>
83 #include <dt-bindings/clock/qcom,gcc-sm8450.h>
84 #include <dt-bindings/clock/qcom,rpmh.h>
85 #include <dt-bindings/interrupt-controller/arm-gic.h>
86 #include <dt-bindings/interconnect/qcom,sm8450.h>
87 #include <dt-bindings/power/qcom,rpmhpd.h>
89 display-subsystem@ae00000 {
90 compatible = "qcom,sm8450-mdss";
91 reg = <0x0ae00000 0x1000>;
94 interconnects = <&mmss_noc MASTER_MDP_DISP &mc_virt SLAVE_EBI1_DISP>,
95 <&mmss_noc MASTER_MDP_DISP &mc_virt SLAVE_EBI1_DISP>,
96 <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_DISPLAY_CFG>;
97 interconnect-names = "mdp0-mem",
101 resets = <&dispcc DISP_CC_MDSS_CORE_BCR>;
103 power-domains = <&dispcc MDSS_GDSC>;
105 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
106 <&gcc GCC_DISP_HF_AXI_CLK>,
107 <&gcc GCC_DISP_SF_AXI_CLK>,
108 <&dispcc DISP_CC_MDSS_MDP_CLK>;
109 clock-names = "iface", "bus", "nrt_bus", "core";
111 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
112 interrupt-controller;
113 #interrupt-cells = <1>;
115 iommus = <&apps_smmu 0x2800 0x402>;
117 #address-cells = <1>;
121 display-controller@ae01000 {
122 compatible = "qcom,sm8450-dpu";
123 reg = <0x0ae01000 0x8f000>,
125 reg-names = "mdp", "vbif";
127 clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
128 <&gcc GCC_DISP_SF_AXI_CLK>,
129 <&dispcc DISP_CC_MDSS_AHB_CLK>,
130 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
131 <&dispcc DISP_CC_MDSS_MDP_CLK>,
132 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
140 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
141 assigned-clock-rates = <19200000>;
143 operating-points-v2 = <&mdp_opp_table>;
144 power-domains = <&rpmhpd RPMHPD_MMCX>;
146 interrupt-parent = <&mdss>;
150 #address-cells = <1>;
155 dpu_intf1_out: endpoint {
156 remote-endpoint = <&dsi0_in>;
162 dpu_intf2_out: endpoint {
163 remote-endpoint = <&dsi1_in>;
168 mdp_opp_table: opp-table {
169 compatible = "operating-points-v2";
172 opp-hz = /bits/ 64 <172000000>;
173 required-opps = <&rpmhpd_opp_low_svs_d1>;
177 opp-hz = /bits/ 64 <200000000>;
178 required-opps = <&rpmhpd_opp_low_svs>;
182 opp-hz = /bits/ 64 <325000000>;
183 required-opps = <&rpmhpd_opp_svs>;
187 opp-hz = /bits/ 64 <375000000>;
188 required-opps = <&rpmhpd_opp_svs_l1>;
192 opp-hz = /bits/ 64 <500000000>;
193 required-opps = <&rpmhpd_opp_nom>;
199 compatible = "qcom,sm8450-dsi-ctrl", "qcom,mdss-dsi-ctrl";
200 reg = <0x0ae94000 0x400>;
201 reg-names = "dsi_ctrl";
203 interrupt-parent = <&mdss>;
206 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
207 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
208 <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
209 <&dispcc DISP_CC_MDSS_ESC0_CLK>,
210 <&dispcc DISP_CC_MDSS_AHB_CLK>,
211 <&gcc GCC_DISP_HF_AXI_CLK>;
212 clock-names = "byte",
219 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
220 <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
221 assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>;
223 operating-points-v2 = <&dsi_opp_table>;
224 power-domains = <&rpmhpd RPMHPD_MMCX>;
229 #address-cells = <1>;
233 #address-cells = <1>;
239 remote-endpoint = <&dpu_intf1_out>;
250 dsi_opp_table: opp-table {
251 compatible = "operating-points-v2";
254 opp-hz = /bits/ 64 <160310000>;
255 required-opps = <&rpmhpd_opp_low_svs_d1>;
259 opp-hz = /bits/ 64 <187500000>;
260 required-opps = <&rpmhpd_opp_low_svs>;
264 opp-hz = /bits/ 64 <300000000>;
265 required-opps = <&rpmhpd_opp_svs>;
269 opp-hz = /bits/ 64 <358000000>;
270 required-opps = <&rpmhpd_opp_svs_l1>;
275 dsi0_phy: phy@ae94400 {
276 compatible = "qcom,sm8450-dsi-phy-5nm";
277 reg = <0x0ae94400 0x200>,
280 reg-names = "dsi_phy",
287 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
288 <&rpmhcc RPMH_CXO_CLK>;
289 clock-names = "iface", "ref";
290 vdds-supply = <&vreg_dsi_phy>;
294 compatible = "qcom,sm8450-dsi-ctrl", "qcom,mdss-dsi-ctrl";
295 reg = <0x0ae96000 0x400>;
296 reg-names = "dsi_ctrl";
298 interrupt-parent = <&mdss>;
301 clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>,
302 <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>,
303 <&dispcc DISP_CC_MDSS_PCLK1_CLK>,
304 <&dispcc DISP_CC_MDSS_ESC1_CLK>,
305 <&dispcc DISP_CC_MDSS_AHB_CLK>,
306 <&gcc GCC_DISP_HF_AXI_CLK>;
307 clock-names = "byte",
314 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>,
315 <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>;
316 assigned-clock-parents = <&dsi1_phy 0>, <&dsi1_phy 1>;
318 operating-points-v2 = <&dsi_opp_table>;
319 power-domains = <&rpmhpd RPMHPD_MMCX>;
324 #address-cells = <1>;
328 #address-cells = <1>;
334 remote-endpoint = <&dpu_intf2_out>;
346 dsi1_phy: phy@ae96400 {
347 compatible = "qcom,sm8450-dsi-phy-5nm";
348 reg = <0x0ae96400 0x200>,
351 reg-names = "dsi_phy",
358 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
359 <&rpmhcc RPMH_CXO_CLK>;
360 clock-names = "iface", "ref";
361 vdds-supply = <&vreg_dsi_phy>;