1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
4 $id: http://devicetree.org/schemas/display/msm/qcom,sm8350-dpu.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm SM8350 Display DPU
10 - Robert Foss <robert.foss@linaro.org>
12 $ref: /schemas/display/msm/dpu-common.yaml#
16 const: qcom,sm8350-dpu
20 - description: Address offset and size for mdp register set
21 - description: Address offset and size for vbif register set
30 - description: Display hf axi clock
31 - description: Display sf axi clock
32 - description: Display ahb clock
33 - description: Display lut clock
34 - description: Display core clock
35 - description: Display vsync clock
46 unevaluatedProperties: false
50 #include <dt-bindings/clock/qcom,dispcc-sm8350.h>
51 #include <dt-bindings/clock/qcom,gcc-sm8350.h>
52 #include <dt-bindings/interrupt-controller/arm-gic.h>
53 #include <dt-bindings/interconnect/qcom,sm8350.h>
54 #include <dt-bindings/power/qcom,rpmhpd.h>
56 display-controller@ae01000 {
57 compatible = "qcom,sm8350-dpu";
58 reg = <0x0ae01000 0x8f000>,
60 reg-names = "mdp", "vbif";
62 clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
63 <&gcc GCC_DISP_SF_AXI_CLK>,
64 <&dispcc DISP_CC_MDSS_AHB_CLK>,
65 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
66 <&dispcc DISP_CC_MDSS_MDP_CLK>,
67 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
75 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
76 assigned-clock-rates = <19200000>;
78 operating-points-v2 = <&mdp_opp_table>;
79 power-domains = <&rpmhpd RPMHPD_MMCX>;
81 interrupt-parent = <&mdss>;
90 dpu_intf1_out: endpoint {
91 remote-endpoint = <&dsi0_in>;
96 mdp_opp_table: opp-table {
97 compatible = "operating-points-v2";
100 opp-hz = /bits/ 64 <200000000>;
101 required-opps = <&rpmhpd_opp_low_svs>;
105 opp-hz = /bits/ 64 <300000000>;
106 required-opps = <&rpmhpd_opp_svs>;
110 opp-hz = /bits/ 64 <345000000>;
111 required-opps = <&rpmhpd_opp_svs_l1>;
115 opp-hz = /bits/ 64 <460000000>;
116 required-opps = <&rpmhpd_opp_nom>;