1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
4 $id: http://devicetree.org/schemas/display/msm/qcom,sm8250-mdss.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm SM8250 Display MDSS
10 - Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
13 Device tree bindings for MSM Mobile Display Subsystem(MDSS) that encapsulates
14 sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree
15 bindings of MDSS are mentioned for SM8250 target.
17 $ref: /schemas/display/msm/mdss-common.yaml#
21 const: qcom,sm8250-mdss
25 - description: Display AHB clock from gcc
26 - description: Display hf axi clock
27 - description: Display sf axi clock
28 - description: Display core clock
47 "^display-controller@[0-9a-f]+$":
49 additionalProperties: true
53 const: qcom,sm8250-dpu
55 "^displayport-controller@[0-9a-f]+$":
57 additionalProperties: true
62 - const: qcom,sm8250-dp
63 - const: qcom,sm8350-dp
67 additionalProperties: true
72 - const: qcom,sm8250-dsi-ctrl
73 - const: qcom,mdss-dsi-ctrl
77 additionalProperties: true
81 const: qcom,dsi-phy-7nm
86 unevaluatedProperties: false
90 #include <dt-bindings/clock/qcom,dispcc-sm8250.h>
91 #include <dt-bindings/clock/qcom,gcc-sm8250.h>
92 #include <dt-bindings/clock/qcom,rpmh.h>
93 #include <dt-bindings/interrupt-controller/arm-gic.h>
94 #include <dt-bindings/interconnect/qcom,sm8250.h>
95 #include <dt-bindings/power/qcom,rpmhpd.h>
97 display-subsystem@ae00000 {
98 compatible = "qcom,sm8250-mdss";
99 reg = <0x0ae00000 0x1000>;
102 interconnects = <&mmss_noc MASTER_MDP_PORT0 &mc_virt SLAVE_EBI_CH0>,
103 <&mmss_noc MASTER_MDP_PORT1 &mc_virt SLAVE_EBI_CH0>;
104 interconnect-names = "mdp0-mem", "mdp1-mem";
106 power-domains = <&dispcc MDSS_GDSC>;
108 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
109 <&gcc GCC_DISP_HF_AXI_CLK>,
110 <&gcc GCC_DISP_SF_AXI_CLK>,
111 <&dispcc DISP_CC_MDSS_MDP_CLK>;
112 clock-names = "iface", "bus", "nrt_bus", "core";
114 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
115 interrupt-controller;
116 #interrupt-cells = <1>;
118 iommus = <&apps_smmu 0x820 0x402>;
120 #address-cells = <1>;
124 display-controller@ae01000 {
125 compatible = "qcom,sm8250-dpu";
126 reg = <0x0ae01000 0x8f000>,
128 reg-names = "mdp", "vbif";
130 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
131 <&gcc GCC_DISP_HF_AXI_CLK>,
132 <&dispcc DISP_CC_MDSS_MDP_CLK>,
133 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
134 clock-names = "iface", "bus", "core", "vsync";
136 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
137 assigned-clock-rates = <19200000>;
139 operating-points-v2 = <&mdp_opp_table>;
140 power-domains = <&rpmhpd RPMHPD_MMCX>;
142 interrupt-parent = <&mdss>;
146 #address-cells = <1>;
151 dpu_intf1_out: endpoint {
152 remote-endpoint = <&dsi0_in>;
158 dpu_intf2_out: endpoint {
159 remote-endpoint = <&dsi1_in>;
164 mdp_opp_table: opp-table {
165 compatible = "operating-points-v2";
168 opp-hz = /bits/ 64 <200000000>;
169 required-opps = <&rpmhpd_opp_low_svs>;
173 opp-hz = /bits/ 64 <300000000>;
174 required-opps = <&rpmhpd_opp_svs>;
178 opp-hz = /bits/ 64 <345000000>;
179 required-opps = <&rpmhpd_opp_svs_l1>;
183 opp-hz = /bits/ 64 <460000000>;
184 required-opps = <&rpmhpd_opp_nom>;
190 compatible = "qcom,sm8250-dsi-ctrl", "qcom,mdss-dsi-ctrl";
191 reg = <0x0ae94000 0x400>;
192 reg-names = "dsi_ctrl";
194 interrupt-parent = <&mdss>;
197 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
198 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
199 <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
200 <&dispcc DISP_CC_MDSS_ESC0_CLK>,
201 <&dispcc DISP_CC_MDSS_AHB_CLK>,
202 <&gcc GCC_DISP_HF_AXI_CLK>;
203 clock-names = "byte",
210 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
211 <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
212 assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>;
214 operating-points-v2 = <&dsi_opp_table>;
215 power-domains = <&rpmhpd RPMHPD_MMCX>;
220 #address-cells = <1>;
224 #address-cells = <1>;
230 remote-endpoint = <&dpu_intf1_out>;
241 dsi_opp_table: opp-table {
242 compatible = "operating-points-v2";
245 opp-hz = /bits/ 64 <187500000>;
246 required-opps = <&rpmhpd_opp_low_svs>;
250 opp-hz = /bits/ 64 <300000000>;
251 required-opps = <&rpmhpd_opp_svs>;
255 opp-hz = /bits/ 64 <358000000>;
256 required-opps = <&rpmhpd_opp_svs_l1>;
261 dsi0_phy: phy@ae94400 {
262 compatible = "qcom,dsi-phy-7nm";
263 reg = <0x0ae94400 0x200>,
266 reg-names = "dsi_phy",
273 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
274 <&rpmhcc RPMH_CXO_CLK>;
275 clock-names = "iface", "ref";
276 vdds-supply = <&vreg_dsi_phy>;
280 compatible = "qcom,sm8250-dsi-ctrl", "qcom,mdss-dsi-ctrl";
281 reg = <0x0ae96000 0x400>;
282 reg-names = "dsi_ctrl";
284 interrupt-parent = <&mdss>;
287 clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>,
288 <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>,
289 <&dispcc DISP_CC_MDSS_PCLK1_CLK>,
290 <&dispcc DISP_CC_MDSS_ESC1_CLK>,
291 <&dispcc DISP_CC_MDSS_AHB_CLK>,
292 <&gcc GCC_DISP_HF_AXI_CLK>;
293 clock-names = "byte",
300 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>,
301 <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>;
302 assigned-clock-parents = <&dsi1_phy 0>, <&dsi1_phy 1>;
304 operating-points-v2 = <&dsi_opp_table>;
305 power-domains = <&rpmhpd RPMHPD_MMCX>;
310 #address-cells = <1>;
314 #address-cells = <1>;
320 remote-endpoint = <&dpu_intf2_out>;
332 dsi1_phy: phy@ae96400 {
333 compatible = "qcom,dsi-phy-7nm";
334 reg = <0x0ae96400 0x200>,
337 reg-names = "dsi_phy",
344 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
345 <&rpmhcc RPMH_CXO_CLK>;
346 clock-names = "iface", "ref";
347 vdds-supply = <&vreg_dsi_phy>;