bindings/display/msm/qcom,sm8250-mdss.yaml

   1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
   2 %YAML 1.2
   3 ---
   4 $id: http://devicetree.org/schemas/display/msm/qcom,sm8250-mdss.yaml#
   5 $schema: http://devicetree.org/meta-schemas/core.yaml#
   6
   7 title: Qualcomm SM8250 Display MDSS
   8
   9 maintainers:
  10   - Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
  11
  12 description:
  13   Device tree bindings for MSM Mobile Display Subsystem(MDSS) that encapsulates
  14   sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree
  15   bindings of MDSS are mentioned for SM8250 target.
  16
  17 $ref: /schemas/display/msm/mdss-common.yaml#
  18
  19 properties:
  20   compatible:
  21     const: qcom,sm8250-mdss
  22
  23   clocks:
  24     items:
  25       - description: Display AHB clock from gcc
  26       - description: Display hf axi clock
  27       - description: Display sf axi clock
  28       - description: Display core clock
  29
  30   clock-names:
  31     items:
  32       - const: iface
  33       - const: bus
  34       - const: nrt_bus
  35       - const: core
  36
  37   iommus:
  38     maxItems: 1
  39
  40   interconnects:
  41     maxItems: 2
  42
  43   interconnect-names:
  44     maxItems: 2
  45
  46 patternProperties:
  47   "^display-controller@[0-9a-f]+$":
  48     type: object
  49     additionalProperties: true
  50
  51     properties:
  52       compatible:
  53         const: qcom,sm8250-dpu
  54
  55   "^displayport-controller@[0-9a-f]+$":
  56     type: object
  57     additionalProperties: true
  58
  59     properties:
  60       compatible:
  61         items:
  62           - const: qcom,sm8250-dp
  63           - const: qcom,sm8350-dp
  64
  65   "^dsi@[0-9a-f]+$":
  66     type: object
  67     additionalProperties: true
  68
  69     properties:
  70       compatible:
  71         items:
  72           - const: qcom,sm8250-dsi-ctrl
  73           - const: qcom,mdss-dsi-ctrl
  74
  75   "^phy@[0-9a-f]+$":
  76     type: object
  77     additionalProperties: true
  78
  79     properties:
  80       compatible:
  81         const: qcom,dsi-phy-7nm
  82
  83 required:
  84   - compatible
  85
  86 unevaluatedProperties: false
  87
  88 examples:
  89   - |
  90     #include <dt-bindings/clock/qcom,dispcc-sm8250.h>
  91     #include <dt-bindings/clock/qcom,gcc-sm8250.h>
  92     #include <dt-bindings/clock/qcom,rpmh.h>
  93     #include <dt-bindings/interrupt-controller/arm-gic.h>
  94     #include <dt-bindings/interconnect/qcom,sm8250.h>
  95     #include <dt-bindings/power/qcom,rpmhpd.h>
  96
  97     display-subsystem@ae00000 {
  98         compatible = "qcom,sm8250-mdss";
  99         reg = <0x0ae00000 0x1000>;
 100         reg-names = "mdss";
 101
 102         interconnects = <&mmss_noc MASTER_MDP_PORT0 &mc_virt SLAVE_EBI_CH0>,
 103                         <&mmss_noc MASTER_MDP_PORT1 &mc_virt SLAVE_EBI_CH0>;
 104         interconnect-names = "mdp0-mem", "mdp1-mem";
 105
 106         power-domains = <&dispcc MDSS_GDSC>;
 107
 108         clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
 109                  <&gcc GCC_DISP_HF_AXI_CLK>,
 110                  <&gcc GCC_DISP_SF_AXI_CLK>,
 111                  <&dispcc DISP_CC_MDSS_MDP_CLK>;
 112         clock-names = "iface", "bus", "nrt_bus", "core";
 113
 114         interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
 115         interrupt-controller;
 116         #interrupt-cells = <1>;
 117
 118         iommus = <&apps_smmu 0x820 0x402>;
 119
 120         #address-cells = <1>;
 121         #size-cells = <1>;
 122         ranges;
 123
 124         display-controller@ae01000 {
 125             compatible = "qcom,sm8250-dpu";
 126             reg = <0x0ae01000 0x8f000>,
 127                   <0x0aeb0000 0x2008>;
 128             reg-names = "mdp", "vbif";
 129
 130             clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
 131                      <&gcc GCC_DISP_HF_AXI_CLK>,
 132                      <&dispcc DISP_CC_MDSS_MDP_CLK>,
 133                      <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
 134             clock-names = "iface", "bus", "core", "vsync";
 135
 136             assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
 137             assigned-clock-rates = <19200000>;
 138
 139             operating-points-v2 = <&mdp_opp_table>;
 140             power-domains = <&rpmhpd RPMHPD_MMCX>;
 141
 142             interrupt-parent = <&mdss>;
 143             interrupts = <0>;
 144
 145             ports {
 146                 #address-cells = <1>;
 147                 #size-cells = <0>;
 148
 149                 port@0 {
 150                     reg = <0>;
 151                     dpu_intf1_out: endpoint {
 152                         remote-endpoint = <&dsi0_in>;
 153                     };
 154                 };
 155
 156                 port@1 {
 157                     reg = <1>;
 158                     dpu_intf2_out: endpoint {
 159                         remote-endpoint = <&dsi1_in>;
 160                     };
 161                 };
 162             };
 163
 164             mdp_opp_table: opp-table {
 165                 compatible = "operating-points-v2";
 166
 167                 opp-200000000 {
 168                     opp-hz = /bits/ 64 <200000000>;
 169                     required-opps = <&rpmhpd_opp_low_svs>;
 170                 };
 171
 172                 opp-300000000 {
 173                     opp-hz = /bits/ 64 <300000000>;
 174                     required-opps = <&rpmhpd_opp_svs>;
 175                 };
 176
 177                 opp-345000000 {
 178                     opp-hz = /bits/ 64 <345000000>;
 179                     required-opps = <&rpmhpd_opp_svs_l1>;
 180                 };
 181
 182                 opp-460000000 {
 183                     opp-hz = /bits/ 64 <460000000>;
 184                     required-opps = <&rpmhpd_opp_nom>;
 185                 };
 186             };
 187         };
 188
 189         dsi@ae94000 {
 190             compatible = "qcom,sm8250-dsi-ctrl", "qcom,mdss-dsi-ctrl";
 191             reg = <0x0ae94000 0x400>;
 192             reg-names = "dsi_ctrl";
 193
 194             interrupt-parent = <&mdss>;
 195             interrupts = <4>;
 196
 197             clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
 198                      <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
 199                      <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
 200                      <&dispcc DISP_CC_MDSS_ESC0_CLK>,
 201                      <&dispcc DISP_CC_MDSS_AHB_CLK>,
 202                      <&gcc GCC_DISP_HF_AXI_CLK>;
 203             clock-names = "byte",
 204                           "byte_intf",
 205                           "pixel",
 206                           "core",
 207                           "iface",
 208                           "bus";
 209
 210             assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
 211                               <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
 212             assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>;
 213
 214             operating-points-v2 = <&dsi_opp_table>;
 215             power-domains = <&rpmhpd RPMHPD_MMCX>;
 216
 217             phys = <&dsi0_phy>;
 218             phy-names = "dsi";
 219
 220             #address-cells = <1>;
 221             #size-cells = <0>;
 222
 223             ports {
 224                 #address-cells = <1>;
 225                 #size-cells = <0>;
 226
 227                 port@0 {
 228                     reg = <0>;
 229                     dsi0_in: endpoint {
 230                         remote-endpoint = <&dpu_intf1_out>;
 231                     };
 232                 };
 233
 234                 port@1 {
 235                     reg = <1>;
 236                     dsi0_out: endpoint {
 237                     };
 238                 };
 239             };
 240
 241             dsi_opp_table: opp-table {
 242                 compatible = "operating-points-v2";
 243
 244                 opp-187500000 {
 245                     opp-hz = /bits/ 64 <187500000>;
 246                     required-opps = <&rpmhpd_opp_low_svs>;
 247                 };
 248
 249                 opp-300000000 {
 250                     opp-hz = /bits/ 64 <300000000>;
 251                     required-opps = <&rpmhpd_opp_svs>;
 252                 };
 253
 254                 opp-358000000 {
 255                     opp-hz = /bits/ 64 <358000000>;
 256                     required-opps = <&rpmhpd_opp_svs_l1>;
 257                 };
 258             };
 259         };
 260
 261         dsi0_phy: phy@ae94400 {
 262             compatible = "qcom,dsi-phy-7nm";
 263             reg = <0x0ae94400 0x200>,
 264                   <0x0ae94600 0x280>,
 265                   <0x0ae94900 0x260>;
 266             reg-names = "dsi_phy",
 267                         "dsi_phy_lane",
 268                         "dsi_pll";
 269
 270             #clock-cells = <1>;
 271             #phy-cells = <0>;
 272
 273             clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
 274                      <&rpmhcc RPMH_CXO_CLK>;
 275             clock-names = "iface", "ref";
 276             vdds-supply = <&vreg_dsi_phy>;
 277         };
 278
 279         dsi@ae96000 {
 280             compatible = "qcom,sm8250-dsi-ctrl", "qcom,mdss-dsi-ctrl";
 281             reg = <0x0ae96000 0x400>;
 282             reg-names = "dsi_ctrl";
 283
 284             interrupt-parent = <&mdss>;
 285             interrupts = <5>;
 286
 287             clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>,
 288                      <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>,
 289                      <&dispcc DISP_CC_MDSS_PCLK1_CLK>,
 290                      <&dispcc DISP_CC_MDSS_ESC1_CLK>,
 291                      <&dispcc DISP_CC_MDSS_AHB_CLK>,
 292                      <&gcc GCC_DISP_HF_AXI_CLK>;
 293             clock-names = "byte",
 294                           "byte_intf",
 295                           "pixel",
 296                           "core",
 297                           "iface",
 298                           "bus";
 299
 300             assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>,
 301                               <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>;
 302             assigned-clock-parents = <&dsi1_phy 0>, <&dsi1_phy 1>;
 303
 304             operating-points-v2 = <&dsi_opp_table>;
 305             power-domains = <&rpmhpd RPMHPD_MMCX>;
 306
 307             phys = <&dsi1_phy>;
 308             phy-names = "dsi";
 309
 310             #address-cells = <1>;
 311             #size-cells = <0>;
 312
 313             ports {
 314                 #address-cells = <1>;
 315                 #size-cells = <0>;
 316
 317                 port@0 {
 318                     reg = <0>;
 319                     dsi1_in: endpoint {
 320                         remote-endpoint = <&dpu_intf2_out>;
 321                     };
 322                 };
 323
 324                 port@1 {
 325                     reg = <1>;
 326                     dsi1_out: endpoint {
 327                     };
 328                 };
 329             };
 330         };
 331
 332         dsi1_phy: phy@ae96400 {
 333             compatible = "qcom,dsi-phy-7nm";
 334             reg = <0x0ae96400 0x200>,
 335                   <0x0ae96600 0x280>,
 336                   <0x0ae96900 0x260>;
 337             reg-names = "dsi_phy",
 338                         "dsi_phy_lane",
 339                         "dsi_pll";
 340
 341             #clock-cells = <1>;
 342             #phy-cells = <0>;
 343
 344             clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
 345                      <&rpmhcc RPMH_CXO_CLK>;
 346             clock-names = "iface", "ref";
 347             vdds-supply = <&vreg_dsi_phy>;
 348         };
 349     };
 350 ...