bindings/display/msm/qcom,sm8150-mdss.yaml

   1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
   2 %YAML 1.2
   3 ---
   4 $id: http://devicetree.org/schemas/display/msm/qcom,sm8150-mdss.yaml#
   5 $schema: http://devicetree.org/meta-schemas/core.yaml#
   6
   7 title: Qualcomm SM8150 Display MDSS
   8
   9 maintainers:
  10   - Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
  11
  12 description:
  13   Device tree bindings for MSM Mobile Display Subsystem(MDSS) that encapsulates
  14   sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree
  15   bindings of MDSS are mentioned for SM8150 target.
  16
  17 $ref: /schemas/display/msm/mdss-common.yaml#
  18
  19 properties:
  20   compatible:
  21     items:
  22       - const: qcom,sm8150-mdss
  23
  24   clocks:
  25     items:
  26       - description: Display AHB clock from gcc
  27       - description: Display hf axi clock
  28       - description: Display sf axi clock
  29       - description: Display core clock
  30
  31   clock-names:
  32     items:
  33       - const: iface
  34       - const: bus
  35       - const: nrt_bus
  36       - const: core
  37
  38   iommus:
  39     maxItems: 1
  40
  41   interconnects:
  42     maxItems: 2
  43
  44   interconnect-names:
  45     maxItems: 2
  46
  47 patternProperties:
  48   "^display-controller@[0-9a-f]+$":
  49     type: object
  50     additionalProperties: true
  51
  52     properties:
  53       compatible:
  54         const: qcom,sm8150-dpu
  55
  56   "^displayport-controller@[0-9a-f]+$":
  57     type: object
  58     additionalProperties: true
  59
  60     properties:
  61       compatible:
  62         contains:
  63           const: qcom,sm8150-dp
  64
  65   "^dsi@[0-9a-f]+$":
  66     type: object
  67     additionalProperties: true
  68
  69     properties:
  70       compatible:
  71         items:
  72           - const: qcom,sm8150-dsi-ctrl
  73           - const: qcom,mdss-dsi-ctrl
  74
  75   "^phy@[0-9a-f]+$":
  76     type: object
  77     additionalProperties: true
  78
  79     properties:
  80       compatible:
  81         const: qcom,dsi-phy-7nm-8150
  82
  83 unevaluatedProperties: false
  84
  85 examples:
  86   - |
  87     #include <dt-bindings/clock/qcom,dispcc-sm8150.h>
  88     #include <dt-bindings/clock/qcom,gcc-sm8150.h>
  89     #include <dt-bindings/clock/qcom,rpmh.h>
  90     #include <dt-bindings/interrupt-controller/arm-gic.h>
  91     #include <dt-bindings/interconnect/qcom,sm8150.h>
  92     #include <dt-bindings/power/qcom-rpmpd.h>
  93
  94     display-subsystem@ae00000 {
  95         compatible = "qcom,sm8150-mdss";
  96         reg = <0x0ae00000 0x1000>;
  97         reg-names = "mdss";
  98
  99         interconnects = <&mmss_noc MASTER_MDP_PORT0 &mc_virt SLAVE_EBI_CH0>,
 100                         <&mmss_noc MASTER_MDP_PORT1 &mc_virt SLAVE_EBI_CH0>;
 101         interconnect-names = "mdp0-mem", "mdp1-mem";
 102
 103         power-domains = <&dispcc MDSS_GDSC>;
 104
 105         clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
 106                  <&gcc GCC_DISP_HF_AXI_CLK>,
 107                  <&gcc GCC_DISP_SF_AXI_CLK>,
 108                  <&dispcc DISP_CC_MDSS_MDP_CLK>;
 109         clock-names = "iface", "bus", "nrt_bus", "core";
 110
 111         interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
 112         interrupt-controller;
 113         #interrupt-cells = <1>;
 114
 115         iommus = <&apps_smmu 0x800 0x420>;
 116
 117         #address-cells = <1>;
 118         #size-cells = <1>;
 119         ranges;
 120
 121         display-controller@ae01000 {
 122             compatible = "qcom,sm8150-dpu";
 123             reg = <0x0ae01000 0x8f000>,
 124                   <0x0aeb0000 0x2008>;
 125             reg-names = "mdp", "vbif";
 126
 127             clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
 128                      <&gcc GCC_DISP_HF_AXI_CLK>,
 129                      <&dispcc DISP_CC_MDSS_MDP_CLK>,
 130                      <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
 131             clock-names = "iface", "bus", "core", "vsync";
 132
 133             assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
 134             assigned-clock-rates = <19200000>;
 135
 136             operating-points-v2 = <&mdp_opp_table>;
 137             power-domains = <&rpmhpd SM8150_MMCX>;
 138
 139             interrupt-parent = <&mdss>;
 140             interrupts = <0>;
 141
 142             ports {
 143                 #address-cells = <1>;
 144                 #size-cells = <0>;
 145
 146                 port@0 {
 147                     reg = <0>;
 148                     dpu_intf1_out: endpoint {
 149                         remote-endpoint = <&dsi0_in>;
 150                     };
 151                 };
 152
 153                 port@1 {
 154                     reg = <1>;
 155                     dpu_intf2_out: endpoint {
 156                         remote-endpoint = <&dsi1_in>;
 157                     };
 158                 };
 159             };
 160
 161             mdp_opp_table: opp-table {
 162                 compatible = "operating-points-v2";
 163
 164                 opp-171428571 {
 165                     opp-hz = /bits/ 64 <171428571>;
 166                     required-opps = <&rpmhpd_opp_low_svs>;
 167                 };
 168
 169                 opp-300000000 {
 170                     opp-hz = /bits/ 64 <300000000>;
 171                     required-opps = <&rpmhpd_opp_svs>;
 172                 };
 173
 174                 opp-345000000 {
 175                     opp-hz = /bits/ 64 <345000000>;
 176                     required-opps = <&rpmhpd_opp_svs_l1>;
 177                 };
 178
 179                 opp-460000000 {
 180                     opp-hz = /bits/ 64 <460000000>;
 181                     required-opps = <&rpmhpd_opp_nom>;
 182                 };
 183             };
 184         };
 185
 186         dsi@ae94000 {
 187             compatible = "qcom,sm8150-dsi-ctrl", "qcom,mdss-dsi-ctrl";
 188             reg = <0x0ae94000 0x400>;
 189             reg-names = "dsi_ctrl";
 190
 191             interrupt-parent = <&mdss>;
 192             interrupts = <4>;
 193
 194             clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
 195                      <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
 196                      <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
 197                      <&dispcc DISP_CC_MDSS_ESC0_CLK>,
 198                      <&dispcc DISP_CC_MDSS_AHB_CLK>,
 199                      <&gcc GCC_DISP_HF_AXI_CLK>;
 200             clock-names = "byte",
 201                           "byte_intf",
 202                           "pixel",
 203                           "core",
 204                           "iface",
 205                           "bus";
 206
 207             assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
 208                               <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
 209             assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>;
 210
 211             operating-points-v2 = <&dsi_opp_table>;
 212             power-domains = <&rpmhpd SM8150_MMCX>;
 213
 214             phys = <&dsi0_phy>;
 215             phy-names = "dsi";
 216
 217             #address-cells = <1>;
 218             #size-cells = <0>;
 219
 220             ports {
 221                 #address-cells = <1>;
 222                 #size-cells = <0>;
 223
 224                 port@0 {
 225                     reg = <0>;
 226                     dsi0_in: endpoint {
 227                         remote-endpoint = <&dpu_intf1_out>;
 228                     };
 229                 };
 230
 231                 port@1 {
 232                     reg = <1>;
 233                     dsi0_out: endpoint {
 234                     };
 235                 };
 236             };
 237
 238             dsi_opp_table: opp-table {
 239                 compatible = "operating-points-v2";
 240
 241                 opp-187500000 {
 242                     opp-hz = /bits/ 64 <187500000>;
 243                     required-opps = <&rpmhpd_opp_low_svs>;
 244                 };
 245
 246                 opp-300000000 {
 247                     opp-hz = /bits/ 64 <300000000>;
 248                     required-opps = <&rpmhpd_opp_svs>;
 249                 };
 250
 251                 opp-358000000 {
 252                     opp-hz = /bits/ 64 <358000000>;
 253                     required-opps = <&rpmhpd_opp_svs_l1>;
 254                 };
 255             };
 256         };
 257
 258         dsi0_phy: phy@ae94400 {
 259             compatible = "qcom,dsi-phy-7nm-8150";
 260             reg = <0x0ae94400 0x200>,
 261                   <0x0ae94600 0x280>,
 262                   <0x0ae94900 0x260>;
 263             reg-names = "dsi_phy",
 264                         "dsi_phy_lane",
 265                         "dsi_pll";
 266
 267             #clock-cells = <1>;
 268             #phy-cells = <0>;
 269
 270             clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
 271                      <&rpmhcc RPMH_CXO_CLK>;
 272             clock-names = "iface", "ref";
 273             vdds-supply = <&vreg_dsi_phy>;
 274         };
 275
 276         dsi@ae96000 {
 277             compatible = "qcom,sm8150-dsi-ctrl", "qcom,mdss-dsi-ctrl";
 278             reg = <0x0ae96000 0x400>;
 279             reg-names = "dsi_ctrl";
 280
 281             interrupt-parent = <&mdss>;
 282             interrupts = <5>;
 283
 284             clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>,
 285                      <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>,
 286                      <&dispcc DISP_CC_MDSS_PCLK1_CLK>,
 287                      <&dispcc DISP_CC_MDSS_ESC1_CLK>,
 288                      <&dispcc DISP_CC_MDSS_AHB_CLK>,
 289                      <&gcc GCC_DISP_HF_AXI_CLK>;
 290             clock-names = "byte",
 291                           "byte_intf",
 292                           "pixel",
 293                           "core",
 294                           "iface",
 295                           "bus";
 296
 297             assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>,
 298                               <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>;
 299             assigned-clock-parents = <&dsi1_phy 0>, <&dsi1_phy 1>;
 300
 301             operating-points-v2 = <&dsi_opp_table>;
 302             power-domains = <&rpmhpd SM8150_MMCX>;
 303
 304             phys = <&dsi1_phy>;
 305             phy-names = "dsi";
 306
 307             #address-cells = <1>;
 308             #size-cells = <0>;
 309
 310             ports {
 311                 #address-cells = <1>;
 312                 #size-cells = <0>;
 313
 314                 port@0 {
 315                     reg = <0>;
 316                     dsi1_in: endpoint {
 317                         remote-endpoint = <&dpu_intf2_out>;
 318                     };
 319                 };
 320
 321                 port@1 {
 322                     reg = <1>;
 323                     dsi1_out: endpoint {
 324                     };
 325                 };
 326             };
 327         };
 328
 329         dsi1_phy: phy@ae96400 {
 330             compatible = "qcom,dsi-phy-7nm-8150";
 331             reg = <0x0ae96400 0x200>,
 332                   <0x0ae96600 0x280>,
 333                   <0x0ae96900 0x260>;
 334             reg-names = "dsi_phy",
 335                         "dsi_phy_lane",
 336                         "dsi_pll";
 337
 338             #clock-cells = <1>;
 339             #phy-cells = <0>;
 340
 341             clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
 342                      <&rpmhcc RPMH_CXO_CLK>;
 343             clock-names = "iface", "ref";
 344             vdds-supply = <&vreg_dsi_phy>;
 345         };
 346     };
 347 ...