1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
4 $id: http://devicetree.org/schemas/display/msm/qcom,sm8150-mdss.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm SM8150 Display MDSS
10 - Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
13 Device tree bindings for MSM Mobile Display Subsystem(MDSS) that encapsulates
14 sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree
15 bindings of MDSS are mentioned for SM8150 target.
17 $ref: /schemas/display/msm/mdss-common.yaml#
22 - const: qcom,sm8150-mdss
26 - description: Display AHB clock from gcc
27 - description: Display hf axi clock
28 - description: Display sf axi clock
29 - description: Display core clock
48 "^display-controller@[0-9a-f]+$":
50 additionalProperties: true
54 const: qcom,sm8150-dpu
56 "^displayport-controller@[0-9a-f]+$":
58 additionalProperties: true
67 additionalProperties: true
72 - const: qcom,sm8150-dsi-ctrl
73 - const: qcom,mdss-dsi-ctrl
77 additionalProperties: true
81 const: qcom,dsi-phy-7nm-8150
83 unevaluatedProperties: false
87 #include <dt-bindings/clock/qcom,dispcc-sm8150.h>
88 #include <dt-bindings/clock/qcom,gcc-sm8150.h>
89 #include <dt-bindings/clock/qcom,rpmh.h>
90 #include <dt-bindings/interrupt-controller/arm-gic.h>
91 #include <dt-bindings/interconnect/qcom,sm8150.h>
92 #include <dt-bindings/power/qcom-rpmpd.h>
94 display-subsystem@ae00000 {
95 compatible = "qcom,sm8150-mdss";
96 reg = <0x0ae00000 0x1000>;
99 interconnects = <&mmss_noc MASTER_MDP_PORT0 &mc_virt SLAVE_EBI_CH0>,
100 <&mmss_noc MASTER_MDP_PORT1 &mc_virt SLAVE_EBI_CH0>;
101 interconnect-names = "mdp0-mem", "mdp1-mem";
103 power-domains = <&dispcc MDSS_GDSC>;
105 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
106 <&gcc GCC_DISP_HF_AXI_CLK>,
107 <&gcc GCC_DISP_SF_AXI_CLK>,
108 <&dispcc DISP_CC_MDSS_MDP_CLK>;
109 clock-names = "iface", "bus", "nrt_bus", "core";
111 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
112 interrupt-controller;
113 #interrupt-cells = <1>;
115 iommus = <&apps_smmu 0x800 0x420>;
117 #address-cells = <1>;
121 display-controller@ae01000 {
122 compatible = "qcom,sm8150-dpu";
123 reg = <0x0ae01000 0x8f000>,
125 reg-names = "mdp", "vbif";
127 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
128 <&gcc GCC_DISP_HF_AXI_CLK>,
129 <&dispcc DISP_CC_MDSS_MDP_CLK>,
130 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
131 clock-names = "iface", "bus", "core", "vsync";
133 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
134 assigned-clock-rates = <19200000>;
136 operating-points-v2 = <&mdp_opp_table>;
137 power-domains = <&rpmhpd SM8150_MMCX>;
139 interrupt-parent = <&mdss>;
143 #address-cells = <1>;
148 dpu_intf1_out: endpoint {
149 remote-endpoint = <&dsi0_in>;
155 dpu_intf2_out: endpoint {
156 remote-endpoint = <&dsi1_in>;
161 mdp_opp_table: opp-table {
162 compatible = "operating-points-v2";
165 opp-hz = /bits/ 64 <171428571>;
166 required-opps = <&rpmhpd_opp_low_svs>;
170 opp-hz = /bits/ 64 <300000000>;
171 required-opps = <&rpmhpd_opp_svs>;
175 opp-hz = /bits/ 64 <345000000>;
176 required-opps = <&rpmhpd_opp_svs_l1>;
180 opp-hz = /bits/ 64 <460000000>;
181 required-opps = <&rpmhpd_opp_nom>;
187 compatible = "qcom,sm8150-dsi-ctrl", "qcom,mdss-dsi-ctrl";
188 reg = <0x0ae94000 0x400>;
189 reg-names = "dsi_ctrl";
191 interrupt-parent = <&mdss>;
194 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
195 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
196 <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
197 <&dispcc DISP_CC_MDSS_ESC0_CLK>,
198 <&dispcc DISP_CC_MDSS_AHB_CLK>,
199 <&gcc GCC_DISP_HF_AXI_CLK>;
200 clock-names = "byte",
207 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
208 <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
209 assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>;
211 operating-points-v2 = <&dsi_opp_table>;
212 power-domains = <&rpmhpd SM8150_MMCX>;
217 #address-cells = <1>;
221 #address-cells = <1>;
227 remote-endpoint = <&dpu_intf1_out>;
238 dsi_opp_table: opp-table {
239 compatible = "operating-points-v2";
242 opp-hz = /bits/ 64 <187500000>;
243 required-opps = <&rpmhpd_opp_low_svs>;
247 opp-hz = /bits/ 64 <300000000>;
248 required-opps = <&rpmhpd_opp_svs>;
252 opp-hz = /bits/ 64 <358000000>;
253 required-opps = <&rpmhpd_opp_svs_l1>;
258 dsi0_phy: phy@ae94400 {
259 compatible = "qcom,dsi-phy-7nm-8150";
260 reg = <0x0ae94400 0x200>,
263 reg-names = "dsi_phy",
270 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
271 <&rpmhcc RPMH_CXO_CLK>;
272 clock-names = "iface", "ref";
273 vdds-supply = <&vreg_dsi_phy>;
277 compatible = "qcom,sm8150-dsi-ctrl", "qcom,mdss-dsi-ctrl";
278 reg = <0x0ae96000 0x400>;
279 reg-names = "dsi_ctrl";
281 interrupt-parent = <&mdss>;
284 clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>,
285 <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>,
286 <&dispcc DISP_CC_MDSS_PCLK1_CLK>,
287 <&dispcc DISP_CC_MDSS_ESC1_CLK>,
288 <&dispcc DISP_CC_MDSS_AHB_CLK>,
289 <&gcc GCC_DISP_HF_AXI_CLK>;
290 clock-names = "byte",
297 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>,
298 <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>;
299 assigned-clock-parents = <&dsi1_phy 0>, <&dsi1_phy 1>;
301 operating-points-v2 = <&dsi_opp_table>;
302 power-domains = <&rpmhpd SM8150_MMCX>;
307 #address-cells = <1>;
311 #address-cells = <1>;
317 remote-endpoint = <&dpu_intf2_out>;
329 dsi1_phy: phy@ae96400 {
330 compatible = "qcom,dsi-phy-7nm-8150";
331 reg = <0x0ae96400 0x200>,
334 reg-names = "dsi_phy",
341 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
342 <&rpmhcc RPMH_CXO_CLK>;
343 clock-names = "iface", "ref";
344 vdds-supply = <&vreg_dsi_phy>;