1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
4 $id: http://devicetree.org/schemas/display/msm/qcom,sm6375-mdss.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm SM6375 Display MDSS
10 - Konrad Dybcio <konrad.dybcio@linaro.org>
13 SM6375 MSM Mobile Display Subsystem (MDSS), which encapsulates sub-blocks
14 like DPU display controller, DSI and DP interfaces etc.
16 $ref: /schemas/display/msm/mdss-common.yaml#
20 const: qcom,sm6375-mdss
24 - description: Display AHB clock from gcc
25 - description: Display AHB clock
26 - description: Display core clock
39 - description: Interconnect path from mdp0 port to the data bus
40 - description: Interconnect path from CPU to the reg bus
48 "^display-controller@[0-9a-f]+$":
50 additionalProperties: true
54 const: qcom,sm6375-dpu
58 additionalProperties: true
63 - const: qcom,sm6375-dsi-ctrl
64 - const: qcom,mdss-dsi-ctrl
68 additionalProperties: true
72 const: qcom,sm6375-dsi-phy-7nm
74 unevaluatedProperties: false
78 #include <dt-bindings/clock/qcom,rpmcc.h>
79 #include <dt-bindings/clock/qcom,sm6375-gcc.h>
80 #include <dt-bindings/clock/qcom,sm6375-dispcc.h>
81 #include <dt-bindings/interrupt-controller/arm-gic.h>
82 #include <dt-bindings/power/qcom-rpmpd.h>
84 display-subsystem@5e00000 {
85 compatible = "qcom,sm6375-mdss";
86 reg = <0x05e00000 0x1000>;
89 power-domains = <&dispcc MDSS_GDSC>;
91 clocks = <&gcc GCC_DISP_AHB_CLK>,
92 <&dispcc DISP_CC_MDSS_AHB_CLK>,
93 <&dispcc DISP_CC_MDSS_MDP_CLK>;
94 clock-names = "iface", "ahb", "core";
96 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
98 #interrupt-cells = <1>;
100 iommus = <&apps_smmu 0x820 0x2>;
101 #address-cells = <1>;
105 display-controller@5e01000 {
106 compatible = "qcom,sm6375-dpu";
107 reg = <0x05e01000 0x8e030>,
109 reg-names = "mdp", "vbif";
111 clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
112 <&dispcc DISP_CC_MDSS_AHB_CLK>,
113 <&dispcc DISP_CC_MDSS_ROT_CLK>,
114 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
115 <&dispcc DISP_CC_MDSS_MDP_CLK>,
116 <&dispcc DISP_CC_MDSS_VSYNC_CLK>,
117 <&gcc GCC_DISP_THROTTLE_CORE_CLK>;
126 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
127 assigned-clock-rates = <19200000>;
129 operating-points-v2 = <&mdp_opp_table>;
130 power-domains = <&rpmpd SM6375_VDDCX>;
132 interrupt-parent = <&mdss>;
136 #address-cells = <1>;
141 dpu_intf1_out: endpoint {
142 remote-endpoint = <&dsi0_in>;
149 compatible = "qcom,sm6375-dsi-ctrl", "qcom,mdss-dsi-ctrl";
150 reg = <0x05e94000 0x400>;
151 reg-names = "dsi_ctrl";
153 interrupt-parent = <&mdss>;
156 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
157 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
158 <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
159 <&dispcc DISP_CC_MDSS_ESC0_CLK>,
160 <&dispcc DISP_CC_MDSS_AHB_CLK>,
161 <&gcc GCC_DISP_HF_AXI_CLK>;
162 clock-names = "byte",
169 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
170 <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
171 assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>;
173 operating-points-v2 = <&dsi_opp_table>;
174 power-domains = <&rpmpd SM6375_VDDMX>;
176 phys = <&mdss_dsi0_phy>;
179 #address-cells = <1>;
183 #address-cells = <1>;
189 remote-endpoint = <&dpu_intf1_out>;
201 mdss_dsi0_phy: phy@5e94400 {
202 compatible = "qcom,sm6375-dsi-phy-7nm";
203 reg = <0x05e94400 0x200>,
206 reg-names = "dsi_phy",
213 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
214 <&rpmcc RPM_SMD_XO_CLK_SRC>;
215 clock-names = "iface", "ref";