bindings/display/msm/qcom,sm6350-mdss.yaml

   1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
   2 %YAML 1.2
   3 ---
   4 $id: http://devicetree.org/schemas/display/msm/qcom,sm6350-mdss.yaml#
   5 $schema: http://devicetree.org/meta-schemas/core.yaml#
   6
   7 title: Qualcomm SM6350 Display MDSS
   8
   9 maintainers:
  10   - Krishna Manikandan <quic_mkrishn@quicinc.com>
  11
  12 description:
  13   SM6350 MSM Mobile Display Subsystem (MDSS), which encapsulates sub-blocks
  14   like DPU display controller, DSI and DP interfaces etc.
  15
  16 $ref: /schemas/display/msm/mdss-common.yaml#
  17
  18 properties:
  19   compatible:
  20     const: qcom,sm6350-mdss
  21
  22   clocks:
  23     items:
  24       - description: Display AHB clock from gcc
  25       - description: Display AXI clock from gcc
  26       - description: Display core clock
  27
  28   clock-names:
  29     items:
  30       - const: iface
  31       - const: bus
  32       - const: core
  33
  34   iommus:
  35     maxItems: 1
  36
  37   interconnects:
  38     items:
  39       - description: Interconnect path from mdp0 port to the data bus
  40       - description: Interconnect path from CPU to the reg bus
  41
  42   interconnect-names:
  43     items:
  44       - const: mdp0-mem
  45       - const: cpu-cfg
  46
  47 patternProperties:
  48   "^display-controller@[0-9a-f]+$":
  49     type: object
  50     additionalProperties: true
  51
  52     properties:
  53       compatible:
  54         const: qcom,sm6350-dpu
  55
  56   "^dsi@[0-9a-f]+$":
  57     type: object
  58     additionalProperties: true
  59
  60     properties:
  61       compatible:
  62         items:
  63           - const: qcom,sm6350-dsi-ctrl
  64           - const: qcom,mdss-dsi-ctrl
  65
  66   "^phy@[0-9a-f]+$":
  67     type: object
  68     additionalProperties: true
  69
  70     properties:
  71       compatible:
  72         const: qcom,dsi-phy-10nm
  73
  74 unevaluatedProperties: false
  75
  76 examples:
  77   - |
  78     #include <dt-bindings/clock/qcom,dispcc-sm6350.h>
  79     #include <dt-bindings/clock/qcom,gcc-sm6350.h>
  80     #include <dt-bindings/clock/qcom,rpmh.h>
  81     #include <dt-bindings/interrupt-controller/arm-gic.h>
  82     #include <dt-bindings/power/qcom-rpmpd.h>
  83
  84     display-subsystem@ae00000 {
  85         compatible = "qcom,sm6350-mdss";
  86         reg = <0x0ae00000 0x1000>;
  87         reg-names = "mdss";
  88
  89         power-domains = <&dispcc MDSS_GDSC>;
  90
  91         clocks = <&gcc GCC_DISP_AHB_CLK>,
  92                  <&gcc GCC_DISP_AXI_CLK>,
  93                  <&dispcc DISP_CC_MDSS_MDP_CLK>;
  94         clock-names = "iface", "bus", "core";
  95
  96         interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
  97         interrupt-controller;
  98         #interrupt-cells = <1>;
  99
 100         iommus = <&apps_smmu 0x800 0x2>;
 101         #address-cells = <1>;
 102         #size-cells = <1>;
 103         ranges;
 104
 105         display-controller@ae01000 {
 106             compatible = "qcom,sm6350-dpu";
 107             reg = <0x0ae01000 0x8f000>,
 108                   <0x0aeb0000 0x2008>;
 109             reg-names = "mdp", "vbif";
 110
 111             clocks = <&gcc GCC_DISP_AXI_CLK>,
 112               <&dispcc DISP_CC_MDSS_AHB_CLK>,
 113               <&dispcc DISP_CC_MDSS_ROT_CLK>,
 114               <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
 115               <&dispcc DISP_CC_MDSS_MDP_CLK>,
 116               <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
 117             clock-names = "bus", "iface", "rot", "lut", "core",
 118                     "vsync";
 119
 120             assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>,
 121                               <&dispcc DISP_CC_MDSS_VSYNC_CLK>,
 122                               <&dispcc DISP_CC_MDSS_ROT_CLK>,
 123                               <&dispcc DISP_CC_MDSS_AHB_CLK>;
 124             assigned-clock-rates = <300000000>,
 125                                    <19200000>,
 126                                    <19200000>,
 127                                    <19200000>;
 128
 129             interrupt-parent = <&mdss>;
 130             interrupts = <0>;
 131             operating-points-v2 = <&mdp_opp_table>;
 132             power-domains = <&rpmhpd SM6350_CX>;
 133
 134             ports {
 135                 #address-cells = <1>;
 136                 #size-cells = <0>;
 137
 138                 port@0 {
 139                     reg = <0>;
 140                     dpu_intf1_out: endpoint {
 141                         remote-endpoint = <&dsi0_in>;
 142                     };
 143                 };
 144             };
 145         };
 146
 147         dsi@ae94000 {
 148             compatible = "qcom,sm6350-dsi-ctrl", "qcom,mdss-dsi-ctrl";
 149             reg = <0x0ae94000 0x400>;
 150             reg-names = "dsi_ctrl";
 151
 152             interrupt-parent = <&mdss>;
 153             interrupts = <4>;
 154
 155             clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
 156                      <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
 157                      <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
 158                      <&dispcc DISP_CC_MDSS_ESC0_CLK>,
 159                      <&dispcc DISP_CC_MDSS_AHB_CLK>,
 160                      <&gcc GCC_DISP_AXI_CLK>;
 161             clock-names = "byte",
 162                           "byte_intf",
 163                           "pixel",
 164                           "core",
 165                           "iface",
 166                           "bus";
 167
 168             assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
 169                               <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
 170             assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>;
 171
 172             operating-points-v2 = <&dsi_opp_table>;
 173             power-domains = <&rpmhpd SM6350_MX>;
 174
 175             phys = <&dsi0_phy>;
 176             phy-names = "dsi";
 177
 178             #address-cells = <1>;
 179             #size-cells = <0>;
 180
 181             ports {
 182                 #address-cells = <1>;
 183                 #size-cells = <0>;
 184
 185                 port@0 {
 186                     reg = <0>;
 187                     dsi0_in: endpoint {
 188                         remote-endpoint = <&dpu_intf1_out>;
 189                     };
 190                 };
 191
 192                 port@1 {
 193                     reg = <1>;
 194                     dsi0_out: endpoint {
 195                     };
 196                 };
 197             };
 198         };
 199
 200         dsi0_phy: phy@ae94400 {
 201             compatible = "qcom,dsi-phy-10nm";
 202             reg = <0x0ae94400 0x200>,
 203                   <0x0ae94600 0x280>,
 204                   <0x0ae94a00 0x1e0>;
 205             reg-names = "dsi_phy",
 206                         "dsi_phy_lane",
 207                         "dsi_pll";
 208
 209             #clock-cells = <1>;
 210             #phy-cells = <0>;
 211
 212             clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, <&rpmhcc RPMH_CXO_CLK>;
 213             clock-names = "iface", "ref";
 214         };
 215     };
 216 ...