1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
4 $id: http://devicetree.org/schemas/display/msm/qcom,sm6350-mdss.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm SM6350 Display MDSS
10 - Krishna Manikandan <quic_mkrishn@quicinc.com>
13 SM6350 MSM Mobile Display Subsystem (MDSS), which encapsulates sub-blocks
14 like DPU display controller, DSI and DP interfaces etc.
16 $ref: /schemas/display/msm/mdss-common.yaml#
20 const: qcom,sm6350-mdss
24 - description: Display AHB clock from gcc
25 - description: Display AXI clock from gcc
26 - description: Display core clock
39 - description: Interconnect path from mdp0 port to the data bus
40 - description: Interconnect path from CPU to the reg bus
48 "^display-controller@[0-9a-f]+$":
50 additionalProperties: true
54 const: qcom,sm6350-dpu
58 additionalProperties: true
63 - const: qcom,sm6350-dsi-ctrl
64 - const: qcom,mdss-dsi-ctrl
68 additionalProperties: true
72 const: qcom,dsi-phy-10nm
74 unevaluatedProperties: false
78 #include <dt-bindings/clock/qcom,dispcc-sm6350.h>
79 #include <dt-bindings/clock/qcom,gcc-sm6350.h>
80 #include <dt-bindings/clock/qcom,rpmh.h>
81 #include <dt-bindings/interrupt-controller/arm-gic.h>
82 #include <dt-bindings/power/qcom-rpmpd.h>
84 display-subsystem@ae00000 {
85 compatible = "qcom,sm6350-mdss";
86 reg = <0x0ae00000 0x1000>;
89 power-domains = <&dispcc MDSS_GDSC>;
91 clocks = <&gcc GCC_DISP_AHB_CLK>,
92 <&gcc GCC_DISP_AXI_CLK>,
93 <&dispcc DISP_CC_MDSS_MDP_CLK>;
94 clock-names = "iface", "bus", "core";
96 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
98 #interrupt-cells = <1>;
100 iommus = <&apps_smmu 0x800 0x2>;
101 #address-cells = <1>;
105 display-controller@ae01000 {
106 compatible = "qcom,sm6350-dpu";
107 reg = <0x0ae01000 0x8f000>,
109 reg-names = "mdp", "vbif";
111 clocks = <&gcc GCC_DISP_AXI_CLK>,
112 <&dispcc DISP_CC_MDSS_AHB_CLK>,
113 <&dispcc DISP_CC_MDSS_ROT_CLK>,
114 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
115 <&dispcc DISP_CC_MDSS_MDP_CLK>,
116 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
117 clock-names = "bus", "iface", "rot", "lut", "core",
120 assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>,
121 <&dispcc DISP_CC_MDSS_VSYNC_CLK>,
122 <&dispcc DISP_CC_MDSS_ROT_CLK>,
123 <&dispcc DISP_CC_MDSS_AHB_CLK>;
124 assigned-clock-rates = <300000000>,
129 interrupt-parent = <&mdss>;
131 operating-points-v2 = <&mdp_opp_table>;
132 power-domains = <&rpmhpd SM6350_CX>;
135 #address-cells = <1>;
140 dpu_intf1_out: endpoint {
141 remote-endpoint = <&dsi0_in>;
148 compatible = "qcom,sm6350-dsi-ctrl", "qcom,mdss-dsi-ctrl";
149 reg = <0x0ae94000 0x400>;
150 reg-names = "dsi_ctrl";
152 interrupt-parent = <&mdss>;
155 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
156 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
157 <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
158 <&dispcc DISP_CC_MDSS_ESC0_CLK>,
159 <&dispcc DISP_CC_MDSS_AHB_CLK>,
160 <&gcc GCC_DISP_AXI_CLK>;
161 clock-names = "byte",
168 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
169 <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
170 assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>;
172 operating-points-v2 = <&dsi_opp_table>;
173 power-domains = <&rpmhpd SM6350_MX>;
178 #address-cells = <1>;
182 #address-cells = <1>;
188 remote-endpoint = <&dpu_intf1_out>;
200 dsi0_phy: phy@ae94400 {
201 compatible = "qcom,dsi-phy-10nm";
202 reg = <0x0ae94400 0x200>,
205 reg-names = "dsi_phy",
212 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, <&rpmhcc RPMH_CXO_CLK>;
213 clock-names = "iface", "ref";