bindings/display/msm/qcom,sm6125-mdss.yaml

   1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
   2 %YAML 1.2
   3 ---
   4 $id: http://devicetree.org/schemas/display/msm/qcom,sm6125-mdss.yaml#
   5 $schema: http://devicetree.org/meta-schemas/core.yaml#
   6
   7 title: Qualcomm SM6125 Display MDSS
   8
   9 maintainers:
  10   - Marijn Suijten <marijn.suijten@somainline.org>
  11
  12 description:
  13   SM6125 MSM Mobile Display Subsystem (MDSS), which encapsulates sub-blocks
  14   like DPU display controller, DSI and DP interfaces etc.
  15
  16 $ref: /schemas/display/msm/mdss-common.yaml#
  17
  18 properties:
  19   compatible:
  20     const: qcom,sm6125-mdss
  21
  22   clocks:
  23     items:
  24       - description: Display AHB clock from gcc
  25       - description: Display AHB clock
  26       - description: Display core clock
  27
  28   clock-names:
  29     items:
  30       - const: iface
  31       - const: ahb
  32       - const: core
  33
  34   iommus:
  35     maxItems: 1
  36
  37   interconnects:
  38     items:
  39       - description: Interconnect path from mdp0 port to the data bus
  40       - description: Interconnect path from CPU to the reg bus
  41
  42   interconnect-names:
  43     items:
  44       - const: mdp0-mem
  45       - const: cpu-cfg
  46
  47 patternProperties:
  48   "^display-controller@[0-9a-f]+$":
  49     type: object
  50     additionalProperties: true
  51
  52     properties:
  53       compatible:
  54         const: qcom,sm6125-dpu
  55
  56   "^dsi@[0-9a-f]+$":
  57     type: object
  58     additionalProperties: true
  59
  60     properties:
  61       compatible:
  62         items:
  63           - const: qcom,sm6125-dsi-ctrl
  64           - const: qcom,mdss-dsi-ctrl
  65
  66   "^phy@[0-9a-f]+$":
  67     type: object
  68     additionalProperties: true
  69
  70     properties:
  71       compatible:
  72         const: qcom,sm6125-dsi-phy-14nm
  73
  74 unevaluatedProperties: false
  75
  76 examples:
  77   - |
  78     #include <dt-bindings/clock/qcom,dispcc-sm6125.h>
  79     #include <dt-bindings/clock/qcom,gcc-sm6125.h>
  80     #include <dt-bindings/clock/qcom,rpmcc.h>
  81     #include <dt-bindings/interrupt-controller/arm-gic.h>
  82     #include <dt-bindings/power/qcom-rpmpd.h>
  83
  84     display-subsystem@5e00000 {
  85         compatible = "qcom,sm6125-mdss";
  86         reg = <0x05e00000 0x1000>;
  87         reg-names = "mdss";
  88
  89         interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
  90         interrupt-controller;
  91         #interrupt-cells = <1>;
  92
  93         clocks = <&gcc GCC_DISP_AHB_CLK>,
  94                  <&dispcc DISP_CC_MDSS_AHB_CLK>,
  95                  <&dispcc DISP_CC_MDSS_MDP_CLK>;
  96         clock-names = "iface",
  97                       "ahb",
  98                       "core";
  99
 100         power-domains = <&dispcc MDSS_GDSC>;
 101
 102         iommus = <&apps_smmu 0x400 0x0>;
 103
 104         #address-cells = <1>;
 105         #size-cells = <1>;
 106         ranges;
 107
 108         display-controller@5e01000 {
 109             compatible = "qcom,sm6125-dpu";
 110             reg = <0x05e01000 0x83208>,
 111                   <0x05eb0000 0x2008>;
 112             reg-names = "mdp", "vbif";
 113
 114             interrupt-parent = <&mdss>;
 115             interrupts = <0>;
 116
 117             clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
 118                      <&dispcc DISP_CC_MDSS_AHB_CLK>,
 119                      <&dispcc DISP_CC_MDSS_ROT_CLK>,
 120                      <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
 121                      <&dispcc DISP_CC_MDSS_MDP_CLK>,
 122                      <&dispcc DISP_CC_MDSS_VSYNC_CLK>,
 123                      <&gcc GCC_DISP_THROTTLE_CORE_CLK>;
 124             clock-names = "bus",
 125                           "iface",
 126                           "rot",
 127                           "lut",
 128                           "core",
 129                           "vsync",
 130                           "throttle";
 131             assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
 132             assigned-clock-rates = <19200000>;
 133
 134             operating-points-v2 = <&mdp_opp_table>;
 135             power-domains = <&rpmpd SM6125_VDDCX>;
 136
 137             ports {
 138                 #address-cells = <1>;
 139                 #size-cells = <0>;
 140
 141                 port@0 {
 142                     reg = <0>;
 143                     dpu_intf1_out: endpoint {
 144                         remote-endpoint = <&mdss_dsi0_in>;
 145                     };
 146                 };
 147             };
 148         };
 149
 150         dsi@5e94000 {
 151             compatible = "qcom,sm6125-dsi-ctrl", "qcom,mdss-dsi-ctrl";
 152             reg = <0x05e94000 0x400>;
 153             reg-names = "dsi_ctrl";
 154
 155             interrupt-parent = <&mdss>;
 156             interrupts = <4>;
 157
 158             clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
 159                      <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
 160                      <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
 161                      <&dispcc DISP_CC_MDSS_ESC0_CLK>,
 162                      <&dispcc DISP_CC_MDSS_AHB_CLK>,
 163                      <&gcc GCC_DISP_HF_AXI_CLK>;
 164             clock-names = "byte",
 165                           "byte_intf",
 166                           "pixel",
 167                           "core",
 168                           "iface",
 169                           "bus";
 170             assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
 171                       <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
 172             assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>;
 173
 174             operating-points-v2 = <&dsi_opp_table>;
 175             power-domains = <&rpmpd SM6125_VDDCX>;
 176
 177             phys = <&mdss_dsi0_phy>;
 178             phy-names = "dsi";
 179
 180             #address-cells = <1>;
 181             #size-cells = <0>;
 182
 183             ports {
 184                 #address-cells = <1>;
 185                 #size-cells = <0>;
 186
 187                 port@0 {
 188                     reg = <0>;
 189                     mdss_dsi0_in: endpoint {
 190                         remote-endpoint = <&dpu_intf1_out>;
 191                     };
 192                 };
 193
 194                 port@1 {
 195                     reg = <1>;
 196                     mdss_dsi0_out: endpoint {
 197                     };
 198                 };
 199             };
 200         };
 201
 202         phy@5e94400 {
 203             compatible = "qcom,sm6125-dsi-phy-14nm";
 204             reg = <0x05e94400 0x100>,
 205                   <0x05e94500 0x300>,
 206                   <0x05e94800 0x188>;
 207             reg-names = "dsi_phy",
 208                         "dsi_phy_lane",
 209                         "dsi_pll";
 210
 211             #clock-cells = <1>;
 212             #phy-cells = <0>;
 213
 214             clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
 215                      <&rpmcc RPM_SMD_XO_CLK_SRC>;
 216             clock-names = "iface",
 217                           "ref";
 218
 219             required-opps = <&rpmpd_opp_nom>;
 220             power-domains = <&rpmpd SM6125_VDDMX>;
 221         };
 222     };
 223 ...