1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
4 $id: http://devicetree.org/schemas/display/msm/qcom,sm6125-mdss.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm SM6125 Display MDSS
10 - Marijn Suijten <marijn.suijten@somainline.org>
13 SM6125 MSM Mobile Display Subsystem (MDSS), which encapsulates sub-blocks
14 like DPU display controller, DSI and DP interfaces etc.
16 $ref: /schemas/display/msm/mdss-common.yaml#
20 const: qcom,sm6125-mdss
24 - description: Display AHB clock from gcc
25 - description: Display AHB clock
26 - description: Display core clock
39 - description: Interconnect path from mdp0 port to the data bus
40 - description: Interconnect path from CPU to the reg bus
48 "^display-controller@[0-9a-f]+$":
50 additionalProperties: true
54 const: qcom,sm6125-dpu
58 additionalProperties: true
63 - const: qcom,sm6125-dsi-ctrl
64 - const: qcom,mdss-dsi-ctrl
68 additionalProperties: true
72 const: qcom,sm6125-dsi-phy-14nm
74 unevaluatedProperties: false
78 #include <dt-bindings/clock/qcom,dispcc-sm6125.h>
79 #include <dt-bindings/clock/qcom,gcc-sm6125.h>
80 #include <dt-bindings/clock/qcom,rpmcc.h>
81 #include <dt-bindings/interrupt-controller/arm-gic.h>
82 #include <dt-bindings/power/qcom-rpmpd.h>
84 display-subsystem@5e00000 {
85 compatible = "qcom,sm6125-mdss";
86 reg = <0x05e00000 0x1000>;
89 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
91 #interrupt-cells = <1>;
93 clocks = <&gcc GCC_DISP_AHB_CLK>,
94 <&dispcc DISP_CC_MDSS_AHB_CLK>,
95 <&dispcc DISP_CC_MDSS_MDP_CLK>;
96 clock-names = "iface",
100 power-domains = <&dispcc MDSS_GDSC>;
102 iommus = <&apps_smmu 0x400 0x0>;
104 #address-cells = <1>;
108 display-controller@5e01000 {
109 compatible = "qcom,sm6125-dpu";
110 reg = <0x05e01000 0x83208>,
112 reg-names = "mdp", "vbif";
114 interrupt-parent = <&mdss>;
117 clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
118 <&dispcc DISP_CC_MDSS_AHB_CLK>,
119 <&dispcc DISP_CC_MDSS_ROT_CLK>,
120 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
121 <&dispcc DISP_CC_MDSS_MDP_CLK>,
122 <&dispcc DISP_CC_MDSS_VSYNC_CLK>,
123 <&gcc GCC_DISP_THROTTLE_CORE_CLK>;
131 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
132 assigned-clock-rates = <19200000>;
134 operating-points-v2 = <&mdp_opp_table>;
135 power-domains = <&rpmpd SM6125_VDDCX>;
138 #address-cells = <1>;
143 dpu_intf1_out: endpoint {
144 remote-endpoint = <&mdss_dsi0_in>;
151 compatible = "qcom,sm6125-dsi-ctrl", "qcom,mdss-dsi-ctrl";
152 reg = <0x05e94000 0x400>;
153 reg-names = "dsi_ctrl";
155 interrupt-parent = <&mdss>;
158 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
159 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
160 <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
161 <&dispcc DISP_CC_MDSS_ESC0_CLK>,
162 <&dispcc DISP_CC_MDSS_AHB_CLK>,
163 <&gcc GCC_DISP_HF_AXI_CLK>;
164 clock-names = "byte",
170 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
171 <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
172 assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>;
174 operating-points-v2 = <&dsi_opp_table>;
175 power-domains = <&rpmpd SM6125_VDDCX>;
177 phys = <&mdss_dsi0_phy>;
180 #address-cells = <1>;
184 #address-cells = <1>;
189 mdss_dsi0_in: endpoint {
190 remote-endpoint = <&dpu_intf1_out>;
196 mdss_dsi0_out: endpoint {
203 compatible = "qcom,sm6125-dsi-phy-14nm";
204 reg = <0x05e94400 0x100>,
207 reg-names = "dsi_phy",
214 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
215 <&rpmcc RPM_SMD_XO_CLK_SRC>;
216 clock-names = "iface",
219 required-opps = <&rpmpd_opp_nom>;
220 power-domains = <&rpmpd SM6125_VDDMX>;