bindings/display/msm/qcom,sm6115-mdss.yaml

   1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
   2 %YAML 1.2
   3 ---
   4 $id: http://devicetree.org/schemas/display/msm/qcom,sm6115-mdss.yaml#
   5 $schema: http://devicetree.org/meta-schemas/core.yaml#
   6
   7 title: Qualcomm SM6115 Display MDSS
   8
   9 maintainers:
  10   - Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
  11
  12 description:
  13   Device tree bindings for MSM Mobile Display Subsystem(MDSS) that encapsulates
  14   sub-blocks like DPU display controller and DSI. Device tree bindings of MDSS
  15   are mentioned for SM6115 target.
  16
  17 $ref: /schemas/display/msm/mdss-common.yaml#
  18
  19 properties:
  20   compatible:
  21     const: qcom,sm6115-mdss
  22
  23   clocks:
  24     items:
  25       - description: Display AHB clock from gcc
  26       - description: Display AXI clock
  27       - description: Display core clock
  28
  29   iommus:
  30     maxItems: 2
  31
  32   interconnects:
  33     items:
  34       - description: Interconnect path from mdp0 port to the data bus
  35       - description: Interconnect path from CPU to the reg bus
  36
  37   interconnect-names:
  38     items:
  39       - const: mdp0-mem
  40       - const: cpu-cfg
  41
  42 patternProperties:
  43   "^display-controller@[0-9a-f]+$":
  44     type: object
  45     additionalProperties: true
  46
  47     properties:
  48       compatible:
  49         const: qcom,sm6115-dpu
  50
  51   "^dsi@[0-9a-f]+$":
  52     type: object
  53     additionalProperties: true
  54
  55     properties:
  56       compatible:
  57         oneOf:
  58           - items:
  59               - const: qcom,sm6115-dsi-ctrl
  60               - const: qcom,mdss-dsi-ctrl
  61           - description: Old binding, please don't use
  62             deprecated: true
  63             const: qcom,dsi-ctrl-6g-qcm2290
  64
  65   "^phy@[0-9a-f]+$":
  66     type: object
  67     additionalProperties: true
  68
  69     properties:
  70       compatible:
  71         const: qcom,dsi-phy-14nm-2290
  72
  73 required:
  74   - compatible
  75
  76 unevaluatedProperties: false
  77
  78 examples:
  79   - |
  80     #include <dt-bindings/clock/qcom,sm6115-dispcc.h>
  81     #include <dt-bindings/clock/qcom,gcc-sm6115.h>
  82     #include <dt-bindings/clock/qcom,rpmcc.h>
  83     #include <dt-bindings/interrupt-controller/arm-gic.h>
  84     #include <dt-bindings/power/qcom-rpmpd.h>
  85
  86     display-subsystem@5e00000 {
  87         #address-cells = <1>;
  88         #size-cells = <1>;
  89         compatible = "qcom,sm6115-mdss";
  90         reg = <0x05e00000 0x1000>;
  91         reg-names = "mdss";
  92         power-domains = <&dispcc MDSS_GDSC>;
  93         clocks = <&gcc GCC_DISP_AHB_CLK>,
  94                  <&gcc GCC_DISP_HF_AXI_CLK>,
  95                  <&dispcc DISP_CC_MDSS_MDP_CLK>;
  96
  97         interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
  98         interrupt-controller;
  99         #interrupt-cells = <1>;
 100
 101         iommus = <&apps_smmu 0x420 0x2>,
 102                  <&apps_smmu 0x421 0x0>;
 103         ranges;
 104
 105         display-controller@5e01000 {
 106             compatible = "qcom,sm6115-dpu";
 107             reg = <0x05e01000 0x8f000>,
 108                   <0x05eb0000 0x2008>;
 109             reg-names = "mdp", "vbif";
 110
 111             clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
 112                      <&dispcc DISP_CC_MDSS_AHB_CLK>,
 113                      <&dispcc DISP_CC_MDSS_MDP_CLK>,
 114                      <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
 115                      <&dispcc DISP_CC_MDSS_ROT_CLK>,
 116                      <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
 117             clock-names = "bus", "iface", "core", "lut", "rot", "vsync";
 118
 119             operating-points-v2 = <&mdp_opp_table>;
 120             power-domains = <&rpmpd SM6115_VDDCX>;
 121
 122             interrupt-parent = <&mdss>;
 123             interrupts = <0>;
 124
 125             ports {
 126                 #address-cells = <1>;
 127                 #size-cells = <0>;
 128
 129                 port@0 {
 130                     reg = <0>;
 131                     dpu_intf1_out: endpoint {
 132                         remote-endpoint = <&dsi0_in>;
 133                     };
 134                 };
 135             };
 136         };
 137
 138         dsi@5e94000 {
 139             compatible = "qcom,sm6115-dsi-ctrl", "qcom,mdss-dsi-ctrl";
 140             reg = <0x05e94000 0x400>;
 141             reg-names = "dsi_ctrl";
 142
 143             interrupt-parent = <&mdss>;
 144             interrupts = <4>;
 145
 146             clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
 147                      <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
 148                      <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
 149                      <&dispcc DISP_CC_MDSS_ESC0_CLK>,
 150                      <&dispcc DISP_CC_MDSS_AHB_CLK>,
 151                      <&gcc GCC_DISP_HF_AXI_CLK>;
 152             clock-names = "byte",
 153                           "byte_intf",
 154                           "pixel",
 155                           "core",
 156                           "iface",
 157                           "bus";
 158             assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
 159             assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>;
 160
 161             operating-points-v2 = <&dsi_opp_table>;
 162             power-domains = <&rpmpd SM6115_VDDCX>;
 163             phys = <&dsi0_phy>;
 164
 165             #address-cells = <1>;
 166             #size-cells = <0>;
 167
 168             ports {
 169                 #address-cells = <1>;
 170                 #size-cells = <0>;
 171
 172                 port@0 {
 173                     reg = <0>;
 174                     dsi0_in: endpoint {
 175                         remote-endpoint = <&dpu_intf1_out>;
 176                     };
 177                 };
 178
 179                 port@1 {
 180                     reg = <1>;
 181                     dsi0_out: endpoint {
 182                     };
 183                 };
 184             };
 185         };
 186
 187         dsi0_phy: phy@5e94400 {
 188             compatible = "qcom,dsi-phy-14nm-2290";
 189             reg = <0x05e94400 0x100>,
 190                   <0x05e94500 0x300>,
 191                   <0x05e94800 0x188>;
 192             reg-names = "dsi_phy",
 193                         "dsi_phy_lane",
 194                         "dsi_pll";
 195
 196             #clock-cells = <1>;
 197             #phy-cells = <0>;
 198
 199             clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, <&rpmcc RPM_SMD_XO_CLK_SRC>;
 200             clock-names = "iface", "ref";
 201         };
 202     };
 203 ...