1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
4 $id: http://devicetree.org/schemas/display/msm/qcom,sdm845-mdss.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm SDM845 Display MDSS
10 - Krishna Manikandan <quic_mkrishn@quicinc.com>
13 Device tree bindings for MSM Mobile Display Subsystem(MDSS) that encapsulates
14 sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree
15 bindings of MDSS are mentioned for SDM845 target.
17 $ref: /schemas/display/msm/mdss-common.yaml#
21 const: qcom,sdm845-mdss
25 - description: Display AHB clock from gcc
26 - description: Display core clock
43 "^display-controller@[0-9a-f]+$":
45 additionalProperties: true
49 const: qcom,sdm845-dpu
51 "^displayport-controller@[0-9a-f]+$":
53 additionalProperties: true
61 additionalProperties: true
66 - const: qcom,sdm845-dsi-ctrl
67 - const: qcom,mdss-dsi-ctrl
71 additionalProperties: true
75 const: qcom,dsi-phy-10nm
80 unevaluatedProperties: false
84 #include <dt-bindings/clock/qcom,dispcc-sdm845.h>
85 #include <dt-bindings/clock/qcom,gcc-sdm845.h>
86 #include <dt-bindings/clock/qcom,rpmh.h>
87 #include <dt-bindings/interrupt-controller/arm-gic.h>
88 #include <dt-bindings/power/qcom-rpmpd.h>
90 display-subsystem@ae00000 {
93 compatible = "qcom,sdm845-mdss";
94 reg = <0x0ae00000 0x1000>;
96 power-domains = <&dispcc MDSS_GDSC>;
98 clocks = <&gcc GCC_DISP_AHB_CLK>,
99 <&dispcc DISP_CC_MDSS_MDP_CLK>;
100 clock-names = "iface", "core";
102 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
103 interrupt-controller;
104 #interrupt-cells = <1>;
106 iommus = <&apps_smmu 0x880 0x8>,
107 <&apps_smmu 0xc80 0x8>;
110 display-controller@ae01000 {
111 compatible = "qcom,sdm845-dpu";
112 reg = <0x0ae01000 0x8f000>,
114 reg-names = "mdp", "vbif";
116 clocks = <&gcc GCC_DISP_AXI_CLK>,
117 <&dispcc DISP_CC_MDSS_AHB_CLK>,
118 <&dispcc DISP_CC_MDSS_AXI_CLK>,
119 <&dispcc DISP_CC_MDSS_MDP_CLK>,
120 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
121 clock-names = "gcc-bus", "iface", "bus", "core", "vsync";
123 interrupt-parent = <&mdss>;
125 power-domains = <&rpmhpd SDM845_CX>;
126 operating-points-v2 = <&mdp_opp_table>;
129 #address-cells = <1>;
134 dpu_intf1_out: endpoint {
135 remote-endpoint = <&dsi0_in>;
141 dpu_intf2_out: endpoint {
142 remote-endpoint = <&dsi1_in>;
149 compatible = "qcom,sdm845-dsi-ctrl", "qcom,mdss-dsi-ctrl";
150 reg = <0x0ae94000 0x400>;
151 reg-names = "dsi_ctrl";
153 interrupt-parent = <&mdss>;
156 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
157 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
158 <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
159 <&dispcc DISP_CC_MDSS_ESC0_CLK>,
160 <&dispcc DISP_CC_MDSS_AHB_CLK>,
161 <&dispcc DISP_CC_MDSS_AXI_CLK>;
162 clock-names = "byte",
168 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
169 <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
170 assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>;
172 operating-points-v2 = <&dsi_opp_table>;
173 power-domains = <&rpmhpd SDM845_CX>;
178 #address-cells = <1>;
182 #address-cells = <1>;
188 remote-endpoint = <&dpu_intf1_out>;
200 dsi0_phy: phy@ae94400 {
201 compatible = "qcom,dsi-phy-10nm";
202 reg = <0x0ae94400 0x200>,
205 reg-names = "dsi_phy",
212 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
213 <&rpmhcc RPMH_CXO_CLK>;
214 clock-names = "iface", "ref";
215 vdds-supply = <&vreg_dsi_phy>;
219 compatible = "qcom,sdm845-dsi-ctrl", "qcom,mdss-dsi-ctrl";
220 reg = <0x0ae96000 0x400>;
221 reg-names = "dsi_ctrl";
223 interrupt-parent = <&mdss>;
226 clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>,
227 <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>,
228 <&dispcc DISP_CC_MDSS_PCLK1_CLK>,
229 <&dispcc DISP_CC_MDSS_ESC1_CLK>,
230 <&dispcc DISP_CC_MDSS_AHB_CLK>,
231 <&dispcc DISP_CC_MDSS_AXI_CLK>;
232 clock-names = "byte",
238 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>,
239 <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>;
240 assigned-clock-parents = <&dsi1_phy 0>, <&dsi1_phy 1>;
242 operating-points-v2 = <&dsi_opp_table>;
243 power-domains = <&rpmhpd SDM845_CX>;
248 #address-cells = <1>;
252 #address-cells = <1>;
258 remote-endpoint = <&dpu_intf2_out>;
270 dsi1_phy: phy@ae96400 {
271 compatible = "qcom,dsi-phy-10nm";
272 reg = <0x0ae96400 0x200>,
275 reg-names = "dsi_phy",
282 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
283 <&rpmhcc RPMH_CXO_CLK>;
284 clock-names = "iface", "ref";
285 vdds-supply = <&vreg_dsi_phy>;