bindings/display/msm/qcom,sdm845-mdss.yaml

   1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
   2 %YAML 1.2
   3 ---
   4 $id: http://devicetree.org/schemas/display/msm/qcom,sdm845-mdss.yaml#
   5 $schema: http://devicetree.org/meta-schemas/core.yaml#
   6
   7 title: Qualcomm SDM845 Display MDSS
   8
   9 maintainers:
  10   - Krishna Manikandan <quic_mkrishn@quicinc.com>
  11
  12 description:
  13   Device tree bindings for MSM Mobile Display Subsystem(MDSS) that encapsulates
  14   sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree
  15   bindings of MDSS are mentioned for SDM845 target.
  16
  17 $ref: /schemas/display/msm/mdss-common.yaml#
  18
  19 properties:
  20   compatible:
  21     const: qcom,sdm845-mdss
  22
  23   clocks:
  24     items:
  25       - description: Display AHB clock from gcc
  26       - description: Display core clock
  27
  28   clock-names:
  29     items:
  30       - const: iface
  31       - const: core
  32
  33   iommus:
  34     maxItems: 2
  35
  36   interconnects:
  37     maxItems: 2
  38
  39   interconnect-names:
  40     maxItems: 2
  41
  42 patternProperties:
  43   "^display-controller@[0-9a-f]+$":
  44     type: object
  45     additionalProperties: true
  46
  47     properties:
  48       compatible:
  49         const: qcom,sdm845-dpu
  50
  51   "^displayport-controller@[0-9a-f]+$":
  52     type: object
  53     additionalProperties: true
  54
  55     properties:
  56       compatible:
  57         const: qcom,sdm845-dp
  58
  59   "^dsi@[0-9a-f]+$":
  60     type: object
  61     additionalProperties: true
  62
  63     properties:
  64       compatible:
  65         items:
  66           - const: qcom,sdm845-dsi-ctrl
  67           - const: qcom,mdss-dsi-ctrl
  68
  69   "^phy@[0-9a-f]+$":
  70     type: object
  71     additionalProperties: true
  72
  73     properties:
  74       compatible:
  75         const: qcom,dsi-phy-10nm
  76
  77 required:
  78   - compatible
  79
  80 unevaluatedProperties: false
  81
  82 examples:
  83   - |
  84     #include <dt-bindings/clock/qcom,dispcc-sdm845.h>
  85     #include <dt-bindings/clock/qcom,gcc-sdm845.h>
  86     #include <dt-bindings/clock/qcom,rpmh.h>
  87     #include <dt-bindings/interrupt-controller/arm-gic.h>
  88     #include <dt-bindings/power/qcom-rpmpd.h>
  89
  90     display-subsystem@ae00000 {
  91         #address-cells = <1>;
  92         #size-cells = <1>;
  93         compatible = "qcom,sdm845-mdss";
  94         reg = <0x0ae00000 0x1000>;
  95         reg-names = "mdss";
  96         power-domains = <&dispcc MDSS_GDSC>;
  97
  98         clocks = <&gcc GCC_DISP_AHB_CLK>,
  99                  <&dispcc DISP_CC_MDSS_MDP_CLK>;
 100         clock-names = "iface", "core";
 101
 102         interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
 103         interrupt-controller;
 104         #interrupt-cells = <1>;
 105
 106         iommus = <&apps_smmu 0x880 0x8>,
 107                  <&apps_smmu 0xc80 0x8>;
 108         ranges;
 109
 110         display-controller@ae01000 {
 111             compatible = "qcom,sdm845-dpu";
 112             reg = <0x0ae01000 0x8f000>,
 113                   <0x0aeb0000 0x2008>;
 114             reg-names = "mdp", "vbif";
 115
 116             clocks = <&gcc GCC_DISP_AXI_CLK>,
 117                      <&dispcc DISP_CC_MDSS_AHB_CLK>,
 118                      <&dispcc DISP_CC_MDSS_AXI_CLK>,
 119                      <&dispcc DISP_CC_MDSS_MDP_CLK>,
 120                      <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
 121             clock-names = "gcc-bus", "iface", "bus", "core", "vsync";
 122
 123             interrupt-parent = <&mdss>;
 124             interrupts = <0>;
 125             power-domains = <&rpmhpd SDM845_CX>;
 126             operating-points-v2 = <&mdp_opp_table>;
 127
 128             ports {
 129                 #address-cells = <1>;
 130                 #size-cells = <0>;
 131
 132                 port@0 {
 133                     reg = <0>;
 134                     dpu_intf1_out: endpoint {
 135                         remote-endpoint = <&dsi0_in>;
 136                     };
 137                 };
 138
 139                 port@1 {
 140                     reg = <1>;
 141                     dpu_intf2_out: endpoint {
 142                         remote-endpoint = <&dsi1_in>;
 143                     };
 144                 };
 145             };
 146         };
 147
 148         dsi@ae94000 {
 149             compatible = "qcom,sdm845-dsi-ctrl", "qcom,mdss-dsi-ctrl";
 150             reg = <0x0ae94000 0x400>;
 151             reg-names = "dsi_ctrl";
 152
 153             interrupt-parent = <&mdss>;
 154             interrupts = <4>;
 155
 156             clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
 157                      <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
 158                      <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
 159                      <&dispcc DISP_CC_MDSS_ESC0_CLK>,
 160                      <&dispcc DISP_CC_MDSS_AHB_CLK>,
 161                      <&dispcc DISP_CC_MDSS_AXI_CLK>;
 162             clock-names = "byte",
 163                           "byte_intf",
 164                           "pixel",
 165                           "core",
 166                           "iface",
 167                           "bus";
 168             assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
 169                               <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
 170             assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>;
 171
 172             operating-points-v2 = <&dsi_opp_table>;
 173             power-domains = <&rpmhpd SDM845_CX>;
 174
 175             phys = <&dsi0_phy>;
 176             phy-names = "dsi";
 177
 178             #address-cells = <1>;
 179             #size-cells = <0>;
 180
 181             ports {
 182                 #address-cells = <1>;
 183                 #size-cells = <0>;
 184
 185                 port@0 {
 186                     reg = <0>;
 187                     dsi0_in: endpoint {
 188                         remote-endpoint = <&dpu_intf1_out>;
 189                     };
 190                 };
 191
 192                 port@1 {
 193                     reg = <1>;
 194                     dsi0_out: endpoint {
 195                     };
 196                 };
 197             };
 198         };
 199
 200         dsi0_phy: phy@ae94400 {
 201             compatible = "qcom,dsi-phy-10nm";
 202             reg = <0x0ae94400 0x200>,
 203                   <0x0ae94600 0x280>,
 204                   <0x0ae94a00 0x1e0>;
 205             reg-names = "dsi_phy",
 206                         "dsi_phy_lane",
 207                         "dsi_pll";
 208
 209             #clock-cells = <1>;
 210             #phy-cells = <0>;
 211
 212             clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
 213                      <&rpmhcc RPMH_CXO_CLK>;
 214             clock-names = "iface", "ref";
 215             vdds-supply = <&vreg_dsi_phy>;
 216         };
 217
 218         dsi@ae96000 {
 219             compatible = "qcom,sdm845-dsi-ctrl", "qcom,mdss-dsi-ctrl";
 220             reg = <0x0ae96000 0x400>;
 221             reg-names = "dsi_ctrl";
 222
 223             interrupt-parent = <&mdss>;
 224             interrupts = <5>;
 225
 226             clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>,
 227                      <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>,
 228                      <&dispcc DISP_CC_MDSS_PCLK1_CLK>,
 229                      <&dispcc DISP_CC_MDSS_ESC1_CLK>,
 230                      <&dispcc DISP_CC_MDSS_AHB_CLK>,
 231                      <&dispcc DISP_CC_MDSS_AXI_CLK>;
 232             clock-names = "byte",
 233                           "byte_intf",
 234                           "pixel",
 235                           "core",
 236                           "iface",
 237                           "bus";
 238             assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>,
 239                               <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>;
 240             assigned-clock-parents = <&dsi1_phy 0>, <&dsi1_phy 1>;
 241
 242             operating-points-v2 = <&dsi_opp_table>;
 243             power-domains = <&rpmhpd SDM845_CX>;
 244
 245             phys = <&dsi1_phy>;
 246             phy-names = "dsi";
 247
 248             #address-cells = <1>;
 249             #size-cells = <0>;
 250
 251             ports {
 252                 #address-cells = <1>;
 253                 #size-cells = <0>;
 254
 255                 port@0 {
 256                     reg = <0>;
 257                     dsi1_in: endpoint {
 258                         remote-endpoint = <&dpu_intf2_out>;
 259                     };
 260                 };
 261
 262                 port@1 {
 263                     reg = <1>;
 264                     dsi1_out: endpoint {
 265                     };
 266                 };
 267             };
 268         };
 269
 270         dsi1_phy: phy@ae96400 {
 271             compatible = "qcom,dsi-phy-10nm";
 272             reg = <0x0ae96400 0x200>,
 273                   <0x0ae96600 0x280>,
 274                   <0x0ae96a00 0x10e>;
 275             reg-names = "dsi_phy",
 276                         "dsi_phy_lane",
 277                         "dsi_pll";
 278
 279             #clock-cells = <1>;
 280             #phy-cells = <0>;
 281
 282             clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
 283                      <&rpmhcc RPMH_CXO_CLK>;
 284             clock-names = "iface", "ref";
 285             vdds-supply = <&vreg_dsi_phy>;
 286         };
 287     };
 288 ...