1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
4 $id: http://devicetree.org/schemas/display/msm/qcom,sc8280xp-mdss.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm SC8280XP Mobile Display Subsystem
10 - Bjorn Andersson <andersson@kernel.org>
13 Device tree bindings for MSM Mobile Display Subsystem (MDSS) that encapsulates
14 sub-blocks like DPU display controller, DSI and DP interfaces etc.
16 $ref: /schemas/display/msm/mdss-common.yaml#
20 const: qcom,sc8280xp-mdss
24 - description: Display AHB clock from gcc
25 - description: Display AHB clock from dispcc
26 - description: Display core clock
35 "^display-controller@[0-9a-f]+$":
37 additionalProperties: true
41 const: qcom,sc8280xp-dpu
43 "^displayport-controller@[0-9a-f]+$":
45 additionalProperties: true
53 unevaluatedProperties: false
57 #include <dt-bindings/clock/qcom,dispcc-sc8280xp.h>
58 #include <dt-bindings/clock/qcom,gcc-sc8280xp.h>
59 #include <dt-bindings/interrupt-controller/arm-gic.h>
60 #include <dt-bindings/interconnect/qcom,sc8280xp.h>
61 #include <dt-bindings/power/qcom-rpmpd.h>
63 display-subsystem@ae00000 {
64 compatible = "qcom,sc8280xp-mdss";
65 reg = <0x0ae00000 0x1000>;
68 power-domains = <&dispcc0 MDSS_GDSC>;
70 clocks = <&gcc GCC_DISP_AHB_CLK>,
71 <&dispcc0 DISP_CC_MDSS_AHB_CLK>,
72 <&dispcc0 DISP_CC_MDSS_MDP_CLK>;
73 clock-names = "iface",
77 resets = <&dispcc0 DISP_CC_MDSS_CORE_BCR>;
79 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
81 #interrupt-cells = <1>;
83 interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>,
84 <&mmss_noc MASTER_MDP1 0 &mc_virt SLAVE_EBI1 0>;
85 interconnect-names = "mdp0-mem", "mdp1-mem";
87 iommus = <&apps_smmu 0x1000 0x402>;
93 display-controller@ae01000 {
94 compatible = "qcom,sc8280xp-dpu";
95 reg = <0x0ae01000 0x8f000>,
97 reg-names = "mdp", "vbif";
99 clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
100 <&gcc GCC_DISP_SF_AXI_CLK>,
101 <&dispcc0 DISP_CC_MDSS_AHB_CLK>,
102 <&dispcc0 DISP_CC_MDSS_MDP_LUT_CLK>,
103 <&dispcc0 DISP_CC_MDSS_MDP_CLK>,
104 <&dispcc0 DISP_CC_MDSS_VSYNC_CLK>;
112 assigned-clocks = <&dispcc0 DISP_CC_MDSS_VSYNC_CLK>;
113 assigned-clock-rates = <19200000>;
115 operating-points-v2 = <&mdss0_mdp_opp_table>;
116 power-domains = <&rpmhpd SC8280XP_MMCX>;
118 interrupt-parent = <&mdss0>;
122 #address-cells = <1>;
128 remote-endpoint = <&mdss0_dp0_in>;
135 remote-endpoint = <&mdss0_dp1_in>;
142 remote-endpoint = <&mdss0_dp3_in>;
149 remote-endpoint = <&mdss0_dp2_in>;