1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
4 $id: http://devicetree.org/schemas/display/msm/qcom,sc8280xp-dpu.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm SC8280XP Display Processing Unit
10 - Bjorn Andersson <andersson@kernel.org>
13 Device tree bindings for SC8280XP Display Processing Unit.
15 $ref: /schemas/display/msm/dpu-common.yaml#
19 const: qcom,sc8280xp-dpu
23 - description: Address offset and size for mdp register set
24 - description: Address offset and size for vbif register set
33 - description: Display hf axi clock
34 - description: Display sf axi clock
35 - description: Display ahb clock
36 - description: Display lut clock
37 - description: Display core clock
38 - description: Display vsync clock
49 unevaluatedProperties: false
53 #include <dt-bindings/clock/qcom,dispcc-sc8280xp.h>
54 #include <dt-bindings/clock/qcom,gcc-sc8280xp.h>
55 #include <dt-bindings/interrupt-controller/arm-gic.h>
56 #include <dt-bindings/interconnect/qcom,sc8280xp.h>
57 #include <dt-bindings/power/qcom-rpmpd.h>
59 display-controller@ae01000 {
60 compatible = "qcom,sc8280xp-dpu";
61 reg = <0x0ae01000 0x8f000>,
63 reg-names = "mdp", "vbif";
65 clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
66 <&gcc GCC_DISP_SF_AXI_CLK>,
67 <&dispcc0 DISP_CC_MDSS_AHB_CLK>,
68 <&dispcc0 DISP_CC_MDSS_MDP_LUT_CLK>,
69 <&dispcc0 DISP_CC_MDSS_MDP_CLK>,
70 <&dispcc0 DISP_CC_MDSS_VSYNC_CLK>;
78 assigned-clocks = <&dispcc0 DISP_CC_MDSS_MDP_CLK>,
79 <&dispcc0 DISP_CC_MDSS_VSYNC_CLK>;
80 assigned-clock-rates = <460000000>,
83 operating-points-v2 = <&mdp_opp_table>;
84 power-domains = <&rpmhpd SC8280XP_MMCX>;
86 interrupt-parent = <&mdss0>;
96 remote-endpoint = <&mdss0_dp0_in>;
103 remote-endpoint = <&mdss0_dp1_in>;
110 remote-endpoint = <&mdss0_dp3_in>;
117 remote-endpoint = <&mdss0_dp2_in>;