bindings/display/msm/qcom,sc8280xp-dpu.yaml

   1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
   2 %YAML 1.2
   3 ---
   4 $id: http://devicetree.org/schemas/display/msm/qcom,sc8280xp-dpu.yaml#
   5 $schema: http://devicetree.org/meta-schemas/core.yaml#
   6
   7 title: Qualcomm SC8280XP Display Processing Unit
   8
   9 maintainers:
  10   - Bjorn Andersson <andersson@kernel.org>
  11
  12 description:
  13   Device tree bindings for SC8280XP Display Processing Unit.
  14
  15 $ref: /schemas/display/msm/dpu-common.yaml#
  16
  17 properties:
  18   compatible:
  19     const: qcom,sc8280xp-dpu
  20
  21   reg:
  22     items:
  23       - description: Address offset and size for mdp register set
  24       - description: Address offset and size for vbif register set
  25
  26   reg-names:
  27     items:
  28       - const: mdp
  29       - const: vbif
  30
  31   clocks:
  32     items:
  33       - description: Display hf axi clock
  34       - description: Display sf axi clock
  35       - description: Display ahb clock
  36       - description: Display lut clock
  37       - description: Display core clock
  38       - description: Display vsync clock
  39
  40   clock-names:
  41     items:
  42       - const: bus
  43       - const: nrt_bus
  44       - const: iface
  45       - const: lut
  46       - const: core
  47       - const: vsync
  48
  49 unevaluatedProperties: false
  50
  51 examples:
  52   - |
  53     #include <dt-bindings/clock/qcom,dispcc-sc8280xp.h>
  54     #include <dt-bindings/clock/qcom,gcc-sc8280xp.h>
  55     #include <dt-bindings/interrupt-controller/arm-gic.h>
  56     #include <dt-bindings/interconnect/qcom,sc8280xp.h>
  57     #include <dt-bindings/power/qcom-rpmpd.h>
  58
  59     display-controller@ae01000 {
  60         compatible = "qcom,sc8280xp-dpu";
  61         reg = <0x0ae01000 0x8f000>,
  62               <0x0aeb0000 0x2008>;
  63         reg-names = "mdp", "vbif";
  64
  65         clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
  66                  <&gcc GCC_DISP_SF_AXI_CLK>,
  67                  <&dispcc0 DISP_CC_MDSS_AHB_CLK>,
  68                  <&dispcc0 DISP_CC_MDSS_MDP_LUT_CLK>,
  69                  <&dispcc0 DISP_CC_MDSS_MDP_CLK>,
  70                  <&dispcc0 DISP_CC_MDSS_VSYNC_CLK>;
  71         clock-names = "bus",
  72                       "nrt_bus",
  73                       "iface",
  74                       "lut",
  75                       "core",
  76                       "vsync";
  77
  78         assigned-clocks = <&dispcc0 DISP_CC_MDSS_MDP_CLK>,
  79                           <&dispcc0 DISP_CC_MDSS_VSYNC_CLK>;
  80         assigned-clock-rates = <460000000>,
  81                                <19200000>;
  82
  83         operating-points-v2 = <&mdp_opp_table>;
  84         power-domains = <&rpmhpd SC8280XP_MMCX>;
  85
  86         interrupt-parent = <&mdss0>;
  87         interrupts = <0>;
  88
  89         ports {
  90             #address-cells = <1>;
  91             #size-cells = <0>;
  92
  93             port@0 {
  94                 reg = <0>;
  95                 endpoint {
  96                     remote-endpoint = <&mdss0_dp0_in>;
  97                 };
  98             };
  99
 100             port@4 {
 101                 reg = <4>;
 102                 endpoint {
 103                     remote-endpoint = <&mdss0_dp1_in>;
 104                 };
 105             };
 106
 107             port@5 {
 108                 reg = <5>;
 109                 endpoint {
 110                     remote-endpoint = <&mdss0_dp3_in>;
 111                 };
 112             };
 113
 114             port@6 {
 115                 reg = <6>;
 116                 endpoint {
 117                     remote-endpoint = <&mdss0_dp2_in>;
 118                 };
 119             };
 120         };
 121     };
 122 ...