1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
4 $id: http://devicetree.org/schemas/display/msm/qcom,sc7180-mdss.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm SC7180 Display MDSS
10 - Krishna Manikandan <quic_mkrishn@quicinc.com>
13 Device tree bindings for MSM Mobile Display Subsystem(MDSS) that encapsulates
14 sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree
15 bindings of MDSS are mentioned for SC7180 target.
17 $ref: /schemas/display/msm/mdss-common.yaml#
21 const: qcom,sc7180-mdss
25 - description: Display AHB clock from gcc
26 - description: Display AHB clock from dispcc
27 - description: Display core clock
40 - description: Interconnect path from mdp0 port to the data bus
41 - description: Interconnect path from CPU to the reg bus
49 "^display-controller@[0-9a-f]+$":
51 additionalProperties: true
55 const: qcom,sc7180-dpu
57 "^displayport-controller@[0-9a-f]+$":
59 additionalProperties: true
67 additionalProperties: true
72 - const: qcom,sc7180-dsi-ctrl
73 - const: qcom,mdss-dsi-ctrl
77 additionalProperties: true
81 const: qcom,dsi-phy-10nm
86 unevaluatedProperties: false
90 #include <dt-bindings/clock/qcom,dispcc-sc7180.h>
91 #include <dt-bindings/clock/qcom,gcc-sc7180.h>
92 #include <dt-bindings/clock/qcom,rpmh.h>
93 #include <dt-bindings/interrupt-controller/arm-gic.h>
94 #include <dt-bindings/interconnect/qcom,sdm845.h>
95 #include <dt-bindings/power/qcom-rpmpd.h>
97 display-subsystem@ae00000 {
100 compatible = "qcom,sc7180-mdss";
101 reg = <0xae00000 0x1000>;
103 power-domains = <&dispcc MDSS_GDSC>;
104 clocks = <&gcc GCC_DISP_AHB_CLK>,
105 <&dispcc DISP_CC_MDSS_AHB_CLK>,
106 <&dispcc DISP_CC_MDSS_MDP_CLK>;
107 clock-names = "iface", "ahb", "core";
109 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
110 interrupt-controller;
111 #interrupt-cells = <1>;
113 interconnects = <&mmss_noc MASTER_MDP0 &mc_virt SLAVE_EBI1>,
114 <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_DISPLAY_CFG>;
115 interconnect-names = "mdp0-mem",
118 iommus = <&apps_smmu 0x800 0x2>;
121 display-controller@ae01000 {
122 compatible = "qcom,sc7180-dpu";
123 reg = <0x0ae01000 0x8f000>,
126 reg-names = "mdp", "vbif";
128 clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
129 <&dispcc DISP_CC_MDSS_AHB_CLK>,
130 <&dispcc DISP_CC_MDSS_ROT_CLK>,
131 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
132 <&dispcc DISP_CC_MDSS_MDP_CLK>,
133 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
134 clock-names = "bus", "iface", "rot", "lut", "core",
137 interrupt-parent = <&mdss>;
139 power-domains = <&rpmhpd SC7180_CX>;
140 operating-points-v2 = <&mdp_opp_table>;
143 #address-cells = <1>;
148 dpu_intf1_out: endpoint {
149 remote-endpoint = <&dsi0_in>;
155 dpu_intf0_out: endpoint {
156 remote-endpoint = <&dp_in>;
163 compatible = "qcom,sc7180-dsi-ctrl", "qcom,mdss-dsi-ctrl";
164 reg = <0x0ae94000 0x400>;
165 reg-names = "dsi_ctrl";
167 interrupt-parent = <&mdss>;
170 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
171 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
172 <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
173 <&dispcc DISP_CC_MDSS_ESC0_CLK>,
174 <&dispcc DISP_CC_MDSS_AHB_CLK>,
175 <&gcc GCC_DISP_HF_AXI_CLK>;
176 clock-names = "byte",
183 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
184 assigned-clock-parents = <&dsi_phy 0>, <&dsi_phy 1>;
186 operating-points-v2 = <&dsi_opp_table>;
187 power-domains = <&rpmhpd SC7180_CX>;
192 #address-cells = <1>;
196 #address-cells = <1>;
202 remote-endpoint = <&dpu_intf1_out>;
213 dsi_opp_table: opp-table {
214 compatible = "operating-points-v2";
217 opp-hz = /bits/ 64 <187500000>;
218 required-opps = <&rpmhpd_opp_low_svs>;
222 opp-hz = /bits/ 64 <300000000>;
223 required-opps = <&rpmhpd_opp_svs>;
227 opp-hz = /bits/ 64 <358000000>;
228 required-opps = <&rpmhpd_opp_svs_l1>;
233 dsi_phy: phy@ae94400 {
234 compatible = "qcom,dsi-phy-10nm";
235 reg = <0x0ae94400 0x200>,
238 reg-names = "dsi_phy",
245 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
246 <&rpmhcc RPMH_CXO_CLK>;
247 clock-names = "iface", "ref";
248 vdds-supply = <&vreg_dsi_phy>;
251 displayport-controller@ae90000 {
252 compatible = "qcom,sc7180-dp";
254 reg = <0xae90000 0x200>,
260 interrupt-parent = <&mdss>;
263 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
264 <&dispcc DISP_CC_MDSS_DP_AUX_CLK>,
265 <&dispcc DISP_CC_MDSS_DP_LINK_CLK>,
266 <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>,
267 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>;
268 clock-names = "core_iface", "core_aux", "ctrl_link",
269 "ctrl_link_iface", "stream_pixel";
270 assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>,
271 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>;
272 assigned-clock-parents = <&dp_phy 0>, <&dp_phy 1>;
276 operating-points-v2 = <&dp_opp_table>;
277 power-domains = <&rpmhpd SC7180_CX>;
279 #sound-dai-cells = <0>;
282 #address-cells = <1>;
287 remote-endpoint = <&dpu_intf0_out>;
293 dp_out: endpoint { };
297 dp_opp_table: opp-table {
298 compatible = "operating-points-v2";
301 opp-hz = /bits/ 64 <160000000>;
302 required-opps = <&rpmhpd_opp_low_svs>;
306 opp-hz = /bits/ 64 <270000000>;
307 required-opps = <&rpmhpd_opp_svs>;
311 opp-hz = /bits/ 64 <540000000>;
312 required-opps = <&rpmhpd_opp_svs_l1>;
316 opp-hz = /bits/ 64 <810000000>;
317 required-opps = <&rpmhpd_opp_nom>;