1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
4 $id: http://devicetree.org/schemas/display/msm/qcom,qcm2290-mdss.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm QCM220 Display MDSS
10 - Loic Poulain <loic.poulain@linaro.org>
13 Device tree bindings for MSM Mobile Display Subsystem(MDSS) that encapsulates
14 sub-blocks like DPU display controller and DSI. Device tree bindings of MDSS
15 are mentioned for QCM2290 target.
17 $ref: /schemas/display/msm/mdss-common.yaml#
21 const: qcom,qcm2290-mdss
25 - description: Display AHB clock from gcc
26 - description: Display AXI clock
27 - description: Display core clock
40 - description: Interconnect path from mdp0 port to the data bus
41 - description: Interconnect path from CPU to the reg bus
49 "^display-controller@[0-9a-f]+$":
51 additionalProperties: true
55 const: qcom,qcm2290-dpu
59 additionalProperties: true
64 - const: qcom,qcm2290-dsi-ctrl
65 - const: qcom,mdss-dsi-ctrl
69 additionalProperties: true
73 const: qcom,dsi-phy-14nm-2290
78 unevaluatedProperties: false
82 #include <dt-bindings/clock/qcom,dispcc-qcm2290.h>
83 #include <dt-bindings/clock/qcom,gcc-qcm2290.h>
84 #include <dt-bindings/clock/qcom,rpmcc.h>
85 #include <dt-bindings/interrupt-controller/arm-gic.h>
86 #include <dt-bindings/interconnect/qcom,qcm2290.h>
87 #include <dt-bindings/power/qcom-rpmpd.h>
89 display-subsystem@5e00000 {
92 compatible = "qcom,qcm2290-mdss";
93 reg = <0x05e00000 0x1000>;
95 power-domains = <&dispcc MDSS_GDSC>;
96 clocks = <&gcc GCC_DISP_AHB_CLK>,
97 <&gcc GCC_DISP_HF_AXI_CLK>,
98 <&dispcc DISP_CC_MDSS_MDP_CLK>;
99 clock-names = "iface", "bus", "core";
101 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
102 interrupt-controller;
103 #interrupt-cells = <1>;
105 interconnects = <&mmrt_virt MASTER_MDP0 &bimc SLAVE_EBI1>,
106 <&bimc MASTER_APPSS_PROC &config_noc SLAVE_DISPLAY_CFG>;
107 interconnect-names = "mdp0-mem",
110 iommus = <&apps_smmu 0x420 0x2>,
111 <&apps_smmu 0x421 0x0>;
114 display-controller@5e01000 {
115 compatible = "qcom,qcm2290-dpu";
116 reg = <0x05e01000 0x8f000>,
118 reg-names = "mdp", "vbif";
120 clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
121 <&dispcc DISP_CC_MDSS_AHB_CLK>,
122 <&dispcc DISP_CC_MDSS_MDP_CLK>,
123 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
124 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
125 clock-names = "bus", "iface", "core", "lut", "vsync";
127 operating-points-v2 = <&mdp_opp_table>;
128 power-domains = <&rpmpd QCM2290_VDDCX>;
130 interrupt-parent = <&mdss>;
134 #address-cells = <1>;
139 dpu_intf1_out: endpoint {
140 remote-endpoint = <&dsi0_in>;
147 compatible = "qcom,qcm2290-dsi-ctrl",
148 "qcom,mdss-dsi-ctrl";
149 reg = <0x05e94000 0x400>;
150 reg-names = "dsi_ctrl";
152 interrupt-parent = <&mdss>;
155 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
156 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
157 <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
158 <&dispcc DISP_CC_MDSS_ESC0_CLK>,
159 <&dispcc DISP_CC_MDSS_AHB_CLK>,
160 <&gcc GCC_DISP_HF_AXI_CLK>;
161 clock-names = "byte",
167 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
168 assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>;
170 operating-points-v2 = <&dsi_opp_table>;
171 power-domains = <&rpmpd QCM2290_VDDCX>;
176 #address-cells = <1>;
180 #address-cells = <1>;
186 remote-endpoint = <&dpu_intf1_out>;
198 dsi0_phy: phy@5e94400 {
199 compatible = "qcom,dsi-phy-14nm-2290";
200 reg = <0x05e94400 0x100>,
203 reg-names = "dsi_phy",
210 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, <&rpmcc RPM_SMD_XO_CLK_SRC>;
211 clock-names = "iface", "ref";
212 vcca-supply = <&vreg_dsi_phy>;