1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
4 $id: http://devicetree.org/schemas/display/msm/qcom,mdss.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Mobile Display SubSystem (MDSS)
10 - Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
11 - Rob Clark <robdclark@gmail.com>
14 This is the bindings documentation for the Mobile Display Subsystem(MDSS) that
15 encapsulates sub-blocks like MDP5, DSI, HDMI, eDP, etc.
19 pattern: "^display-subsystem@[0-9a-f]+$"
34 - const: vbif_nrt_phys
39 interrupt-controller: true
47 The MDSS power domain provided by GCC
53 - description: Display abh clock
54 - description: Display axi clock
55 - description: Display vsync clock
56 - description: Display core clock
59 - description: Display abh clock
60 - description: Display core clock
85 - description: MDSS_CORE reset
92 - interrupt-controller
102 "^display-controller@[1-9a-f][0-9a-f]*$":
104 additionalProperties: true
110 "^dsi@[1-9a-f][0-9a-f]*$":
112 additionalProperties: true
116 const: qcom,mdss-dsi-ctrl
118 "^phy@[1-9a-f][0-9a-f]*$":
120 additionalProperties: true
125 - qcom,dsi-phy-14nm-660
126 - qcom,dsi-phy-14nm-8953
128 - qcom,dsi-phy-28nm-8226
129 - qcom,dsi-phy-28nm-hpm
130 - qcom,dsi-phy-28nm-hpm-fam-b
131 - qcom,dsi-phy-28nm-lp
138 "^hdmi-tx@[1-9a-f][0-9a-f]*$":
140 additionalProperties: true
151 additionalProperties: false
155 #include <dt-bindings/clock/qcom,gcc-msm8916.h>
156 #include <dt-bindings/interrupt-controller/arm-gic.h>
157 display-subsystem@1a00000 {
158 compatible = "qcom,mdss";
159 reg = <0x1a00000 0x1000>,
161 reg-names = "mdss_phys", "vbif_phys";
163 power-domains = <&gcc MDSS_GDSC>;
165 clocks = <&gcc GCC_MDSS_AHB_CLK>,
166 <&gcc GCC_MDSS_AXI_CLK>,
167 <&gcc GCC_MDSS_VSYNC_CLK>;
168 clock-names = "iface",
172 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
174 interrupt-controller;
175 #interrupt-cells = <1>;
177 #address-cells = <1>;
181 display-controller@1a01000 {
182 compatible = "qcom,msm8916-mdp5", "qcom,mdp5";
183 reg = <0x01a01000 0x89000>;
184 reg-names = "mdp_phys";
186 interrupt-parent = <&mdss>;
189 clocks = <&gcc GCC_MDSS_AHB_CLK>,
190 <&gcc GCC_MDSS_AXI_CLK>,
191 <&gcc GCC_MDSS_MDP_CLK>,
192 <&gcc GCC_MDSS_VSYNC_CLK>;
193 clock-names = "iface",
198 iommus = <&apps_iommu 4>;
201 #address-cells = <1>;
206 mdp5_intf1_out: endpoint {
207 remote-endpoint = <&dsi0_in>;