1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
5 $id: http://devicetree.org/schemas/display/msm/gpu.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Adreno or Snapdragon GPUs
11 - Rob Clark <robdclark@gmail.com>
17 The driver is parsing the compat string for Adreno to
18 figure out the chip-id.
20 - pattern: '^qcom,adreno-[0-9a-f][0-9a-f][0-9a-f][0-9a-f][0-9a-f][0-9a-f][0-9a-f][0-9a-f]$'
23 The driver is parsing the compat string for Adreno to
24 figure out the gpu-id and patch level.
26 - pattern: '^qcom,adreno-[3-7][0-9][0-9]\.[0-9]$'
29 The driver is parsing the compat string for Imageon to
30 figure out the gpu-id and patch level.
32 - pattern: '^amd,imageon-200\.[0-1]$'
68 $ref: /schemas/types.yaml#/definitions/phandle-array
74 phandles to one or more reserved on-chip SRAM regions.
75 phandle to the On Chip Memory (OCMEM) that's present on some a3xx and
76 a4xx Snapdragon SoCs. See
77 Documentation/devicetree/bindings/sram/qcom,ocmem.yaml
79 operating-points-v2: true
88 additionalProperties: false
90 For a5xx and a6xx devices this node contains a memory-region that
91 points to reserved memory to store the zap shader that can be used to
92 help bring the GPU out of secure mode.
99 Default name of the firmware to load to the remote processor.
108 description: efuse registers
112 $ref: /schemas/types.yaml#/definitions/phandle
114 For GMU attached devices a phandle to the GMU device that will
115 control the power for the GPU.
123 additionalProperties: false
130 pattern: '^qcom,adreno-[3-5][0-9][0-9]\.[0-9]$'
142 description: GPU Core clock
144 description: GPU Interface clock
146 description: GPU Memory clock
148 description: GPU Memory Interface clock
149 - const: alt_mem_iface
150 description: GPU Alternative Memory Interface clock
152 description: GPU 3D engine clock
154 description: GPU RBBM Timer for Adreno 5xx series
156 description: GPU RB Core Power Reduction clock
180 description: GPU Core clock
182 description: GPU Interface clock
184 description: GPU Memory Interface clock
185 - const: alt_mem_iface
186 description: GPU Alternative Memory Interface clock
188 description: CX GMU clock
190 description: GPUCC clocksource clock
195 - const: kgsl_3d0_reg_memory
206 pattern: '^qcom,adreno-[67][0-9][0-9]\.[0-9]$'
208 then: # Starting with A6xx, the clocks are usually defined in the GMU node
216 - const: kgsl_3d0_reg_memory
225 #include <dt-bindings/clock/qcom,mmcc-msm8974.h>
226 #include <dt-bindings/clock/qcom,rpmcc.h>
227 #include <dt-bindings/interrupt-controller/irq.h>
228 #include <dt-bindings/interrupt-controller/arm-gic.h>
231 compatible = "qcom,adreno-330.2", "qcom,adreno";
233 reg = <0xfdb00000 0x10000>;
234 reg-names = "kgsl_3d0_reg_memory";
236 clock-names = "core", "iface", "mem_iface";
237 clocks = <&mmcc OXILI_GFX3D_CLK>,
238 <&mmcc OXILICX_AHB_CLK>,
239 <&mmcc OXILICX_AXI_CLK>;
241 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
242 interrupt-names = "kgsl_3d0_irq";
245 power-domains = <&mmcc OXILICX_GDSC>;
246 operating-points-v2 = <&gpu_opp_table>;
247 iommus = <&gpu_iommu 0>;
248 #cooling-cells = <2>;
252 compatible = "qcom,msm8974-ocmem";
254 reg = <0xfdd00000 0x2000>,
255 <0xfec00000 0x180000>;
256 reg-names = "ctrl", "mem";
258 clocks = <&rpmcc RPM_SMD_OCMEMGX_CLK>,
259 <&mmcc OCMEMCX_OCMEMNOC_CLK>;
260 clock-names = "core", "iface";
262 #address-cells = <1>;
264 ranges = <0 0xfec00000 0x100000>;
266 gpu_sram: gpu-sram@0 {
267 reg = <0x0 0x100000>;
272 // Example a6xx (with GMU):
274 #include <dt-bindings/clock/qcom,gpucc-sdm845.h>
275 #include <dt-bindings/clock/qcom,gcc-sdm845.h>
276 #include <dt-bindings/power/qcom-rpmpd.h>
277 #include <dt-bindings/interrupt-controller/irq.h>
278 #include <dt-bindings/interrupt-controller/arm-gic.h>
279 #include <dt-bindings/interconnect/qcom,sdm845.h>
282 #address-cells = <2>;
285 zap_shader_region: gpu@8f200000 {
286 compatible = "shared-dma-pool";
287 reg = <0x0 0x90b00000 0x0 0xa00000>;
293 compatible = "qcom,adreno-630.2", "qcom,adreno";
295 reg = <0x5000000 0x40000>, <0x509e000 0x10>;
296 reg-names = "kgsl_3d0_reg_memory", "cx_mem";
298 #cooling-cells = <2>;
300 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
302 iommus = <&adreno_smmu 0>;
304 operating-points-v2 = <&gpu_opp_table>;
306 interconnects = <&rsc_hlos MASTER_GFX3D &rsc_hlos SLAVE_EBI1>;
307 interconnect-names = "gfx-mem";
311 gpu_opp_table: opp-table {
312 compatible = "operating-points-v2";
315 opp-hz = /bits/ 64 <430000000>;
316 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
317 opp-peak-kBps = <5412000>;
321 opp-hz = /bits/ 64 <355000000>;
322 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
323 opp-peak-kBps = <3072000>;
327 opp-hz = /bits/ 64 <267000000>;
328 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
329 opp-peak-kBps = <3072000>;
333 opp-hz = /bits/ 64 <180000000>;
334 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
335 opp-peak-kBps = <1804000>;
340 memory-region = <&zap_shader_region>;
341 firmware-name = "/*(DEBLOBBED)*/";