1 # SPDX-License-Identifier: GPL-2.0-only
2 # Copyright 2019-2020, The Linux Foundation, All Rights Reserved
6 $id: http://devicetree.org/schemas/display/msm/gmu.yaml#
7 $schema: http://devicetree.org/meta-schemas/core.yaml#
9 title: GMU attached to certain Adreno GPUs
12 - Rob Clark <robdclark@gmail.com>
15 These bindings describe the Graphics Management Unit (GMU) that is attached
16 to members of the Adreno A6xx GPU family. The GMU provides on-device power
17 management and support to improve power efficiency and reduce the load on
24 - pattern: '^qcom,adreno-gmu-[67][0-9][0-9]\.[0-9]$'
25 - const: qcom,adreno-gmu
26 - const: qcom,adreno-gmu-wrapper
46 - description: GMU HFI interrupt
47 - description: GMU interrupt
56 - description: CX power domain
57 - description: GX power domain
68 $ref: /schemas/types.yaml#/definitions/phandle
69 description: Reference to the AOSS side-channel message RAM
71 operating-points-v2: true
83 additionalProperties: false
91 - qcom,adreno-gmu-618.0
92 - qcom,adreno-gmu-630.2
97 - description: Core GMU registers
98 - description: GMU PDC registers
99 - description: GMU PDC sequence registers
107 - description: GMU clock
108 - description: GPU CX clock
109 - description: GPU AXI clock
110 - description: GPU MEMNOC clock
123 - qcom,adreno-gmu-635.0
124 - qcom,adreno-gmu-660.1
129 - description: Core GMU registers
130 - description: Resource controller registers
131 - description: GMU PDC registers
139 - description: GMU clock
140 - description: GPU CX clock
141 - description: GPU AXI clock
142 - description: GPU MEMNOC clock
143 - description: GPU AHB clock
144 - description: GPU HUB CX clock
145 - description: GPU SMMU vote clock
161 - qcom,adreno-gmu-640.1
166 - description: Core GMU registers
167 - description: GMU PDC registers
168 - description: GMU PDC sequence registers
180 - qcom,adreno-gmu-650.2
185 - description: Core GMU registers
186 - description: Resource controller registers
187 - description: GMU PDC registers
188 - description: GMU PDC sequence registers
201 - qcom,adreno-gmu-640.1
202 - qcom,adreno-gmu-650.2
207 - description: GPU AHB clock
208 - description: GMU clock
209 - description: GPU CX clock
210 - description: GPU AXI clock
211 - description: GPU MEMNOC clock
225 - qcom,adreno-gmu-730.1
226 - qcom,adreno-gmu-740.1
231 - description: Core GMU registers
232 - description: Resource controller registers
233 - description: GMU PDC registers
241 - description: GPU AHB clock
242 - description: GMU clock
243 - description: GPU CX clock
244 - description: GPU AXI clock
245 - description: GPU MEMNOC clock
246 - description: GMU HUB clock
247 - description: GPUSS DEMET clock
265 const: qcom,adreno-gmu-wrapper
270 - description: GMU wrapper register space
281 - operating-points-v2
285 #include <dt-bindings/clock/qcom,gpucc-sdm845.h>
286 #include <dt-bindings/clock/qcom,gcc-sdm845.h>
287 #include <dt-bindings/interrupt-controller/irq.h>
288 #include <dt-bindings/interrupt-controller/arm-gic.h>
291 compatible = "qcom,adreno-gmu-630.2", "qcom,adreno-gmu";
293 reg = <0x506a000 0x30000>,
296 reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq";
298 clocks = <&gpucc GPU_CC_CX_GMU_CLK>,
299 <&gpucc GPU_CC_CXO_CLK>,
300 <&gcc GCC_DDRSS_GPU_AXI_CLK>,
301 <&gcc GCC_GPU_MEMNOC_GFX_CLK>;
302 clock-names = "gmu", "cxo", "axi", "memnoc";
304 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
305 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
306 interrupt-names = "hfi", "gmu";
308 power-domains = <&gpucc GPU_CX_GDSC>,
309 <&gpucc GPU_GX_GDSC>;
310 power-domain-names = "cx", "gx";
312 iommus = <&adreno_smmu 5>;
313 operating-points-v2 = <&gmu_opp_table>;
316 gmu_wrapper: gmu@596a000 {
317 compatible = "qcom,adreno-gmu-wrapper";
318 reg = <0x0596a000 0x30000>;
320 power-domains = <&gpucc GPU_CX_GDSC>,
321 <&gpucc GPU_GX_GDSC>;
322 power-domain-names = "cx", "gx";