1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
4 $id: http://devicetree.org/schemas/display/msm/dsi-controller-main.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Display DSI controller
10 - Krishna Manikandan <quic_mkrishn@quicinc.com>
17 - qcom,apq8064-dsi-ctrl
18 - qcom,msm8226-dsi-ctrl
19 - qcom,msm8916-dsi-ctrl
20 - qcom,msm8953-dsi-ctrl
21 - qcom,msm8974-dsi-ctrl
22 - qcom,msm8996-dsi-ctrl
23 - qcom,msm8998-dsi-ctrl
24 - qcom,qcm2290-dsi-ctrl
25 - qcom,sc7180-dsi-ctrl
26 - qcom,sc7280-dsi-ctrl
27 - qcom,sdm660-dsi-ctrl
28 - qcom,sdm670-dsi-ctrl
29 - qcom,sdm845-dsi-ctrl
30 - qcom,sm6115-dsi-ctrl
31 - qcom,sm6125-dsi-ctrl
32 - qcom,sm6350-dsi-ctrl
33 - qcom,sm6375-dsi-ctrl
34 - qcom,sm8150-dsi-ctrl
35 - qcom,sm8250-dsi-ctrl
36 - qcom,sm8350-dsi-ctrl
37 - qcom,sm8450-dsi-ctrl
38 - qcom,sm8550-dsi-ctrl
39 - qcom,sm8650-dsi-ctrl
40 - const: qcom,mdss-dsi-ctrl
42 - qcom,dsi-ctrl-6g-qcm2290
43 - qcom,mdss-dsi-ctrl # This should always come with an SoC-specific compatible
57 Several clocks are used, depending on the variant. Typical ones are::
58 - bus:: Display AHB clock.
59 - byte:: Display byte clock.
60 - byte_intf:: Display byte interface clock.
61 - core:: Display core clock.
62 - core_mss:: Core MultiMedia SubSystem clock.
63 - iface:: Display AXI clock.
64 - mdp_core:: MDP Core clock.
66 - pixel:: Display pixel clock.
82 description: A phandle to mmss_sfpb syscon node (only for DSIv2).
83 $ref: /schemas/types.yaml#/definitions/phandle
88 Indicates if the DSI controller is driving a panel which needs
94 Indicates if the DSI controller is the master DSI controller when
95 qcom,dual-dsi-mode enabled.
100 Indicates if the DSI controller needs to sync the other DSI controller
101 with MIPI DCS commands when qcom,dual-dsi-mode enabled.
107 Parents of "byte" and "pixel" for the given platform.
108 For DSIv2 platforms this should contain "byte", "esc", "src" and
111 assigned-clock-parents:
115 The Byte clock and Pixel clock PLL outputs provided by a DSI PHY block.
120 operating-points-v2: true
126 $ref: /schemas/graph.yaml#/properties/ports
128 Contains DSI controller input and output ports as children, each
129 containing one endpoint subnode.
133 $ref: /schemas/graph.yaml#/$defs/port-base
134 unevaluatedProperties: false
136 Input endpoints of the controller.
139 $ref: /schemas/media/video-interfaces.yaml#
140 unevaluatedProperties: false
149 $ref: /schemas/graph.yaml#/$defs/port-base
150 unevaluatedProperties: false
152 Output endpoints of the controller.
155 $ref: /schemas/media/video-interfaces.yaml#
156 unevaluatedProperties: false
170 Phandle to vdd regulator device node
174 Phandle to REFGEN regulator device node
178 Phandle to vdd regulator device node
201 - assigned-clock-parents
205 - $ref: ../dsi-controller.yaml#
211 - qcom,apq8064-dsi-ctrl
231 - qcom,msm8916-dsi-ctrl
250 - qcom,msm8953-dsi-ctrl
269 - qcom,msm8226-dsi-ctrl
270 - qcom,msm8974-dsi-ctrl
290 - qcom,msm8996-dsi-ctrl
310 - qcom,msm8998-dsi-ctrl
311 - qcom,sm6125-dsi-ctrl
312 - qcom,sm6350-dsi-ctrl
331 - qcom,sc7180-dsi-ctrl
332 - qcom,sc7280-dsi-ctrl
333 - qcom,sm8150-dsi-ctrl
334 - qcom,sm8250-dsi-ctrl
335 - qcom,sm8350-dsi-ctrl
336 - qcom,sm8450-dsi-ctrl
337 - qcom,sm8550-dsi-ctrl
338 - qcom,sm8650-dsi-ctrl
357 - qcom,sdm660-dsi-ctrl
379 - qcom,sdm845-dsi-ctrl
380 - qcom,sm6115-dsi-ctrl
381 - qcom,sm6375-dsi-ctrl
395 unevaluatedProperties: false
399 #include <dt-bindings/interrupt-controller/arm-gic.h>
400 #include <dt-bindings/clock/qcom,dispcc-sdm845.h>
401 #include <dt-bindings/clock/qcom,gcc-sdm845.h>
402 #include <dt-bindings/power/qcom-rpmpd.h>
405 compatible = "qcom,sc7180-dsi-ctrl", "qcom,mdss-dsi-ctrl";
406 reg = <0x0ae94000 0x400>;
407 reg-names = "dsi_ctrl";
409 #address-cells = <1>;
412 interrupt-parent = <&mdss>;
415 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
416 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
417 <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
418 <&dispcc DISP_CC_MDSS_ESC0_CLK>,
419 <&dispcc DISP_CC_MDSS_AHB_CLK>,
420 <&dispcc DISP_CC_MDSS_AXI_CLK>;
421 clock-names = "byte",
431 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
432 assigned-clock-parents = <&dsi_phy 0>, <&dsi_phy 1>;
434 power-domains = <&rpmhpd SC7180_CX>;
435 operating-points-v2 = <&dsi_opp_table>;
438 #address-cells = <1>;
444 remote-endpoint = <&dpu_intf1_out>;
451 remote-endpoint = <&sn65dsi86_in>;
452 data-lanes = <0 1 2 3>;