1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/display/msm/dp-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: MSM Display Port Controller
10 - Kuogee Hsieh <quic_khsieh@quicinc.com>
13 Device tree bindings for DisplayPort host controller for MSM targets
14 that are compatible with VESA DisplayPort interface specification.
36 - const: qcom,sm8350-dp
41 - description: ahb register block
42 - description: aux register block
43 - description: link register block
44 - description: p0 register block
45 - description: p1 register block
52 - description: AHB clock to enable register access
53 - description: Display Port AUX clock
54 - description: Display Port Link clock
55 - description: Link interface clock between DP and PHY
56 - description: Display Port Pixel clock
63 - const: ctrl_link_iface
68 - description: link clock source
69 - description: pixel clock source
71 assigned-clock-parents:
73 - description: phy 0 parent
74 - description: phy 1 parent
83 operating-points-v2: true
92 $ref: /schemas/display/dp-aux-bus.yaml#
95 $ref: /schemas/types.yaml#/definitions/uint32-array
111 $ref: /schemas/graph.yaml#/properties/ports
114 $ref: /schemas/graph.yaml#/properties/port
115 description: Input endpoint of the controller
118 $ref: /schemas/graph.yaml#/$defs/port-base
119 unevaluatedProperties: false
120 description: Output endpoint of the controller
123 $ref: /schemas/media/video-interfaces.yaml#
124 unevaluatedProperties: false
136 enum: [ 1620000000, 2700000000, 5400000000, 8100000000 ]
154 # AUX BUS does not exist on DP controllers
155 # Audio output also is present only on DP output
156 # p1 regions is present on DP, but not on eDP
167 "#sound-dai-cells": false
176 additionalProperties: false
180 #include <dt-bindings/interrupt-controller/arm-gic.h>
181 #include <dt-bindings/clock/qcom,dispcc-sc7180.h>
182 #include <dt-bindings/power/qcom-rpmpd.h>
184 displayport-controller@ae90000 {
185 compatible = "qcom,sc7180-dp";
186 reg = <0xae90000 0x200>,
191 interrupt-parent = <&mdss>;
193 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
194 <&dispcc DISP_CC_MDSS_DP_AUX_CLK>,
195 <&dispcc DISP_CC_MDSS_DP_LINK_CLK>,
196 <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>,
197 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>;
198 clock-names = "core_iface", "core_aux",
200 "ctrl_link_iface", "stream_pixel";
202 assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>,
203 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>;
205 assigned-clock-parents = <&dp_phy 0>, <&dp_phy 1>;
210 #sound-dai-cells = <0>;
212 power-domains = <&rpmhpd SC7180_CX>;
215 #address-cells = <1>;
221 remote-endpoint = <&dpu_intf0_out>;
228 remote-endpoint = <&typec>;
230 link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>;