1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/display/bridge/ti,sn65dsi86.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: SN65DSI86 DSI to eDP bridge chip
10 - Sandeep Panda <spanda@codeaurora.org>
13 The Texas Instruments SN65DSI86 bridge takes MIPI DSI in and outputs eDP.
14 https://www.ti.com/general/docs/lit/getliterature.tsp?genericPartNumber=sn65dsi86&fileType=pdf
25 description: GPIO specifier for bridge_en pin (active high).
29 description: GPIO specifier for GPIO1 pin on bridge (active low).
34 Set if the HPD line on the bridge isn't hooked up to anything or is
38 description: A 1.8V supply that powers the digital IOs.
41 description: A 1.8V supply that powers the DisplayPort PLL.
44 description: A 1.2V supply that powers the analog circuits.
47 description: A 1.2V supply that powers the digital core.
55 Clock specifier for input reference clock. The reference clock rate must
56 be 12 MHz, 19.2 MHz, 26 MHz, 27 MHz or 38.4 MHz.
65 First cell is pin number, second cell is flags. GPIO pin numbers are
66 1-based to match the datasheet. See ../../gpio/gpio.txt for more
71 description: See ../../pwm/pwm.yaml for description of the cell formats.
74 $ref: /schemas/display/dp-aux-bus.yaml#
77 $ref: /schemas/graph.yaml#/properties/ports
81 $ref: /schemas/graph.yaml#/properties/port
83 Video port for MIPI DSI input
86 $ref: /schemas/graph.yaml#/$defs/port-base
87 unevaluatedProperties: false
89 Video port for eDP output (panel or connector).
93 $ref: /schemas/media/video-interfaces.yaml#
94 unevaluatedProperties: false
107 If you have 1 logical lane the bridge supports routing
108 to either port 0 or port 1. Port 0 is suggested.
118 If you have 2 logical lanes the bridge supports
119 reordering but only on physical ports 0 and 1.
131 If you have 4 logical lanes the bridge supports
132 reordering in any way.
143 lane-polarities: [data-lanes]
158 additionalProperties: false
162 #include <dt-bindings/clock/qcom,rpmh.h>
163 #include <dt-bindings/gpio/gpio.h>
164 #include <dt-bindings/interrupt-controller/irq.h>
167 #address-cells = <1>;
171 compatible = "ti,sn65dsi86";
174 interrupt-parent = <&tlmm>;
175 interrupts = <10 IRQ_TYPE_LEVEL_HIGH>;
177 enable-gpios = <&tlmm 102 GPIO_ACTIVE_HIGH>;
179 vpll-supply = <&src_pp1800_s4a>;
180 vccio-supply = <&src_pp1800_s4a>;
181 vcca-supply = <&src_pp1200_l2a>;
182 vcc-supply = <&src_pp1200_l2a>;
184 clocks = <&rpmhcc RPMH_LN_BB_CLK2>;
185 clock-names = "refclk";
190 #address-cells = <1>;
196 remote-endpoint = <&dsi0_out>;
202 sn65dsi86_out: endpoint {
203 remote-endpoint = <&panel_in_edp>;
210 compatible = "boe,nv133fhm-n62";
211 power-supply = <&pp3300_dx_edp>;
212 backlight = <&backlight>;
213 hpd-gpios = <&sn65dsi86_bridge 2 GPIO_ACTIVE_HIGH>;
216 panel_in_edp: endpoint {
217 remote-endpoint = <&sn65dsi86_out>;
225 #include <dt-bindings/clock/qcom,rpmh.h>
226 #include <dt-bindings/gpio/gpio.h>
227 #include <dt-bindings/interrupt-controller/irq.h>
230 #address-cells = <1>;
234 compatible = "ti,sn65dsi86";
237 enable-gpios = <&msmgpio 33 GPIO_ACTIVE_HIGH>;
238 suspend-gpios = <&msmgpio 34 GPIO_ACTIVE_LOW>;
240 interrupts-extended = <&gpio3 4 IRQ_TYPE_EDGE_FALLING>;
242 vccio-supply = <&pm8916_l17>;
243 vcca-supply = <&pm8916_l6>;
244 vpll-supply = <&pm8916_l17>;
245 vcc-supply = <&pm8916_l6>;
247 clock-names = "refclk";
248 clocks = <&input_refclk>;
251 #address-cells = <1>;
257 edp_bridge_in: endpoint {
258 remote-endpoint = <&dsi_out>;
265 edp_bridge_out: endpoint {
266 data-lanes = <2 1 3 0>;
267 lane-polarities = <0 1 0 1>;
268 remote-endpoint = <&edp_panel_in>;