bindings/display/bridge/ti,sn65dsi86.yaml

   1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
   2 %YAML 1.2
   3 ---
   4 $id: http://devicetree.org/schemas/display/bridge/ti,sn65dsi86.yaml#
   5 $schema: http://devicetree.org/meta-schemas/core.yaml#
   6
   7 title: SN65DSI86 DSI to eDP bridge chip
   8
   9 maintainers:
  10   - Sandeep Panda <spanda@codeaurora.org>
  11
  12 description: |
  13   The Texas Instruments SN65DSI86 bridge takes MIPI DSI in and outputs eDP.
  14   https://www.ti.com/general/docs/lit/getliterature.tsp?genericPartNumber=sn65dsi86&fileType=pdf
  15
  16 properties:
  17   compatible:
  18     const: ti,sn65dsi86
  19
  20   reg:
  21     enum: [ 0x2c, 0x2d ]
  22
  23   enable-gpios:
  24     maxItems: 1
  25     description: GPIO specifier for bridge_en pin (active high).
  26
  27   suspend-gpios:
  28     maxItems: 1
  29     description: GPIO specifier for GPIO1 pin on bridge (active low).
  30
  31   no-hpd:
  32     type: boolean
  33     description:
  34       Set if the HPD line on the bridge isn't hooked up to anything or is
  35       otherwise unusable.
  36
  37   vccio-supply:
  38     description: A 1.8V supply that powers the digital IOs.
  39
  40   vpll-supply:
  41     description: A 1.8V supply that powers the DisplayPort PLL.
  42
  43   vcca-supply:
  44     description: A 1.2V supply that powers the analog circuits.
  45
  46   vcc-supply:
  47     description: A 1.2V supply that powers the digital core.
  48
  49   interrupts:
  50     maxItems: 1
  51
  52   clocks:
  53     maxItems: 1
  54     description:
  55       Clock specifier for input reference clock. The reference clock rate must
  56       be 12 MHz, 19.2 MHz, 26 MHz, 27 MHz or 38.4 MHz.
  57
  58   clock-names:
  59     const: refclk
  60
  61   gpio-controller: true
  62   '#gpio-cells':
  63     const: 2
  64     description:
  65       First cell is pin number, second cell is flags.  GPIO pin numbers are
  66       1-based to match the datasheet.  See ../../gpio/gpio.txt for more
  67       information.
  68
  69   '#pwm-cells':
  70     const: 1
  71     description: See ../../pwm/pwm.yaml for description of the cell formats.
  72
  73   aux-bus:
  74     $ref: /schemas/display/dp-aux-bus.yaml#
  75
  76   ports:
  77     $ref: /schemas/graph.yaml#/properties/ports
  78
  79     properties:
  80       port@0:
  81         $ref: /schemas/graph.yaml#/properties/port
  82         description:
  83           Video port for MIPI DSI input
  84
  85       port@1:
  86         $ref: /schemas/graph.yaml#/$defs/port-base
  87         unevaluatedProperties: false
  88         description:
  89           Video port for eDP output (panel or connector).
  90
  91         properties:
  92           endpoint:
  93             $ref: /schemas/media/video-interfaces.yaml#
  94             unevaluatedProperties: false
  95
  96             properties:
  97               data-lanes:
  98                 oneOf:
  99                   - minItems: 1
 100                     maxItems: 1
 101                     uniqueItems: true
 102                     items:
 103                       enum:
 104                         - 0
 105                         - 1
 106                     description:
 107                       If you have 1 logical lane the bridge supports routing
 108                       to either port 0 or port 1.  Port 0 is suggested.
 109
 110                   - minItems: 2
 111                     maxItems: 2
 112                     uniqueItems: true
 113                     items:
 114                       enum:
 115                         - 0
 116                         - 1
 117                     description:
 118                       If you have 2 logical lanes the bridge supports
 119                       reordering but only on physical ports 0 and 1.
 120
 121                   - minItems: 4
 122                     maxItems: 4
 123                     uniqueItems: true
 124                     items:
 125                       enum:
 126                         - 0
 127                         - 1
 128                         - 2
 129                         - 3
 130                     description:
 131                       If you have 4 logical lanes the bridge supports
 132                       reordering in any way.
 133
 134               lane-polarities:
 135                 minItems: 1
 136                 maxItems: 4
 137                 items:
 138                   enum:
 139                     - 0
 140                     - 1
 141
 142             dependencies:
 143               lane-polarities: [data-lanes]
 144
 145     required:
 146       - port@0
 147       - port@1
 148
 149 required:
 150   - compatible
 151   - reg
 152   - vccio-supply
 153   - vpll-supply
 154   - vcca-supply
 155   - vcc-supply
 156   - ports
 157
 158 additionalProperties: false
 159
 160 examples:
 161   - |
 162     #include <dt-bindings/clock/qcom,rpmh.h>
 163     #include <dt-bindings/gpio/gpio.h>
 164     #include <dt-bindings/interrupt-controller/irq.h>
 165
 166     i2c {
 167       #address-cells = <1>;
 168       #size-cells = <0>;
 169
 170       bridge@2d {
 171         compatible = "ti,sn65dsi86";
 172         reg = <0x2d>;
 173
 174         interrupt-parent = <&tlmm>;
 175         interrupts = <10 IRQ_TYPE_LEVEL_HIGH>;
 176
 177         enable-gpios = <&tlmm 102 GPIO_ACTIVE_HIGH>;
 178
 179         vpll-supply = <&src_pp1800_s4a>;
 180         vccio-supply = <&src_pp1800_s4a>;
 181         vcca-supply = <&src_pp1200_l2a>;
 182         vcc-supply = <&src_pp1200_l2a>;
 183
 184         clocks = <&rpmhcc RPMH_LN_BB_CLK2>;
 185         clock-names = "refclk";
 186
 187         no-hpd;
 188
 189         ports {
 190           #address-cells = <1>;
 191           #size-cells = <0>;
 192
 193           port@0 {
 194             reg = <0>;
 195             endpoint {
 196               remote-endpoint = <&dsi0_out>;
 197             };
 198           };
 199
 200           port@1 {
 201             reg = <1>;
 202             sn65dsi86_out: endpoint {
 203               remote-endpoint = <&panel_in_edp>;
 204             };
 205           };
 206         };
 207
 208         aux-bus {
 209           panel {
 210             compatible = "boe,nv133fhm-n62";
 211             power-supply = <&pp3300_dx_edp>;
 212             backlight = <&backlight>;
 213             hpd-gpios = <&sn65dsi86_bridge 2 GPIO_ACTIVE_HIGH>;
 214
 215             port {
 216               panel_in_edp: endpoint {
 217                 remote-endpoint = <&sn65dsi86_out>;
 218               };
 219             };
 220           };
 221         };
 222       };
 223     };
 224   - |
 225     #include <dt-bindings/clock/qcom,rpmh.h>
 226     #include <dt-bindings/gpio/gpio.h>
 227     #include <dt-bindings/interrupt-controller/irq.h>
 228
 229     i2c {
 230       #address-cells = <1>;
 231       #size-cells = <0>;
 232
 233       bridge@2d {
 234         compatible = "ti,sn65dsi86";
 235         reg = <0x2d>;
 236
 237         enable-gpios = <&msmgpio 33 GPIO_ACTIVE_HIGH>;
 238         suspend-gpios = <&msmgpio 34 GPIO_ACTIVE_LOW>;
 239
 240         interrupts-extended = <&gpio3 4 IRQ_TYPE_EDGE_FALLING>;
 241
 242         vccio-supply = <&pm8916_l17>;
 243         vcca-supply = <&pm8916_l6>;
 244         vpll-supply = <&pm8916_l17>;
 245         vcc-supply = <&pm8916_l6>;
 246
 247         clock-names = "refclk";
 248         clocks = <&input_refclk>;
 249
 250         ports {
 251           #address-cells = <1>;
 252           #size-cells = <0>;
 253
 254           port@0 {
 255             reg = <0>;
 256
 257             edp_bridge_in: endpoint {
 258               remote-endpoint = <&dsi_out>;
 259             };
 260           };
 261
 262           port@1 {
 263             reg = <1>;
 264
 265             edp_bridge_out: endpoint {
 266               data-lanes = <2 1 3 0>;
 267               lane-polarities = <0 1 0 1>;
 268               remote-endpoint = <&edp_panel_in>;
 269             };
 270           };
 271         };
 272       };
 273     };