1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/display/bridge/samsung,mipi-dsim.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Samsung MIPI DSIM bridge controller
10 - Inki Dae <inki.dae@samsung.com>
11 - Jagan Teki <jagan@amarulasolutions.com>
12 - Marek Szyprowski <m.szyprowski@samsung.com>
15 Samsung MIPI DSIM bridge controller can be found it on Exynos
16 and i.MX8M Mini/Nano/Plus SoC's.
22 - samsung,exynos3250-mipi-dsi
23 - samsung,exynos4210-mipi-dsi
24 - samsung,exynos5410-mipi-dsi
25 - samsung,exynos5422-mipi-dsi
26 - samsung,exynos5433-mipi-dsi
27 - fsl,imx8mm-mipi-dsim
28 - fsl,imx8mp-mipi-dsim
30 - const: fsl,imx8mn-mipi-dsim
31 - const: fsl,imx8mm-mipi-dsim
54 $ref: /schemas/types.yaml#/definitions/uint32
55 description: phandle to the samsung phy-type
61 $ref: /schemas/types.yaml#/definitions/phandle
62 description: phandle to the associated samsung power domain
65 description: MIPI DSIM Core voltage supply (e.g. 1.1V)
68 description: MIPI DSIM I/O and PLL voltage supply (e.g. 1.8V)
70 samsung,burst-clock-frequency:
71 $ref: /schemas/types.yaml#/definitions/uint32
73 DSIM high speed burst mode frequency. If absent,
74 the pixel clock from the attached device or bridge
77 samsung,esc-clock-frequency:
78 $ref: /schemas/types.yaml#/definitions/uint32
80 DSIM escape mode frequency.
82 samsung,pll-clock-frequency:
83 $ref: /schemas/types.yaml#/definitions/uint32
85 DSIM oscillator clock frequency. If absent, the clock frequency
86 of sclk_mipi will be used instead.
95 $ref: /schemas/graph.yaml#/properties/ports
99 $ref: /schemas/graph.yaml#/properties/port
101 Input port node to receive pixel data from the
102 display controller. Exactly one endpoint must be
106 $ref: /schemas/graph.yaml#/$defs/port-base
107 unevaluatedProperties: false
109 DSI output port node to the panel or the next bridge
114 $ref: /schemas/media/video-interfaces.yaml#
115 unevaluatedProperties: false
129 The Samsung MIPI DSI IP requires that all the data lanes have
133 lane-polarities: [data-lanes]
141 - samsung,esc-clock-frequency
144 - $ref: ../dsi-controller.yaml#
149 const: samsung,exynos5433-mipi-dsi
159 - const: phyclk_mipidphy0_bitclkdiv8
160 - const: phyclk_mipidphy0_rxclkesc0
161 - const: sclk_rgb_vclk_to_dsim0
177 const: samsung,exynos5410-mipi-dsi
197 const: samsung,exynos4210-mipi-dsi
217 const: samsung,exynos3250-mipi-dsi
234 additionalProperties:
239 #include <dt-bindings/clock/exynos5433.h>
240 #include <dt-bindings/gpio/gpio.h>
241 #include <dt-bindings/interrupt-controller/arm-gic.h>
244 compatible = "samsung,exynos5433-mipi-dsi";
245 reg = <0x13900000 0xC0>;
246 interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
247 phys = <&mipi_phy 1>;
249 clocks = <&cmu_disp CLK_PCLK_DSIM0>,
250 <&cmu_disp CLK_PHYCLK_MIPIDPHY0_BITCLKDIV8>,
251 <&cmu_disp CLK_PHYCLK_MIPIDPHY0_RXCLKESC0>,
252 <&cmu_disp CLK_SCLK_RGB_VCLK_TO_DSIM0>,
253 <&cmu_disp CLK_SCLK_DSIM0>;
254 clock-names = "bus_clk",
255 "phyclk_mipidphy0_bitclkdiv8",
256 "phyclk_mipidphy0_rxclkesc0",
257 "sclk_rgb_vclk_to_dsim0",
259 power-domains = <&pd_disp>;
260 vddcore-supply = <&ldo6_reg>;
261 vddio-supply = <&ldo7_reg>;
262 samsung,burst-clock-frequency = <512000000>;
263 samsung,esc-clock-frequency = <16000000>;
264 samsung,pll-clock-frequency = <24000000>;
265 pinctrl-names = "default";
266 pinctrl-0 = <&te_irq>;
269 #address-cells = <1>;
275 dsi_to_mic: endpoint {
276 remote-endpoint = <&mic_to_dsi>;