bindings/display/bridge/renesas,dsi.yaml

   1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
   2 %YAML 1.2
   3 ---
   4 $id: http://devicetree.org/schemas/display/bridge/renesas,dsi.yaml#
   5 $schema: http://devicetree.org/meta-schemas/core.yaml#
   6
   7 title: Renesas RZ/G2L MIPI DSI Encoder
   8
   9 maintainers:
  10   - Biju Das <biju.das.jz@bp.renesas.com>
  11
  12 description: |
  13   This binding describes the MIPI DSI encoder embedded in the Renesas
  14   RZ/G2L alike family of SoC's. The encoder can operate in DSI mode, with
  15   up to four data lanes.
  16
  17 allOf:
  18   - $ref: /schemas/display/dsi-controller.yaml#
  19
  20 properties:
  21   compatible:
  22     items:
  23       - enum:
  24           - renesas,r9a07g044-mipi-dsi # RZ/G2{L,LC}
  25           - renesas,r9a07g054-mipi-dsi # RZ/V2L
  26       - const: renesas,rzg2l-mipi-dsi
  27
  28   reg:
  29     maxItems: 1
  30
  31   interrupts:
  32     items:
  33       - description: Sequence operation channel 0 interrupt
  34       - description: Sequence operation channel 1 interrupt
  35       - description: Video-Input operation channel 1 interrupt
  36       - description: DSI Packet Receive interrupt
  37       - description: DSI Fatal Error interrupt
  38       - description: DSI D-PHY PPI interrupt
  39       - description: Debug interrupt
  40
  41   interrupt-names:
  42     items:
  43       - const: seq0
  44       - const: seq1
  45       - const: vin1
  46       - const: rcv
  47       - const: ferr
  48       - const: ppi
  49       - const: debug
  50
  51   clocks:
  52     items:
  53       - description: DSI D-PHY PLL multiplied clock
  54       - description: DSI D-PHY system clock
  55       - description: DSI AXI bus clock
  56       - description: DSI Register access clock
  57       - description: DSI Video clock
  58       - description: DSI D-PHY Escape mode transmit clock
  59
  60   clock-names:
  61     items:
  62       - const: pllclk
  63       - const: sysclk
  64       - const: aclk
  65       - const: pclk
  66       - const: vclk
  67       - const: lpclk
  68
  69   resets:
  70     items:
  71       - description: MIPI_DSI_CMN_RSTB
  72       - description: MIPI_DSI_ARESET_N
  73       - description: MIPI_DSI_PRESET_N
  74
  75   reset-names:
  76     items:
  77       - const: rst
  78       - const: arst
  79       - const: prst
  80
  81   power-domains:
  82     maxItems: 1
  83
  84   ports:
  85     $ref: /schemas/graph.yaml#/properties/ports
  86
  87     properties:
  88       port@0:
  89         $ref: /schemas/graph.yaml#/properties/port
  90         description: Parallel input port
  91
  92       port@1:
  93         $ref: /schemas/graph.yaml#/$defs/port-base
  94         unevaluatedProperties: false
  95         description: DSI output port
  96
  97         properties:
  98           endpoint:
  99             $ref: /schemas/media/video-interfaces.yaml#
 100             unevaluatedProperties: false
 101
 102             properties:
 103               data-lanes:
 104                 description: array of physical DSI data lane indexes.
 105                 minItems: 1
 106                 items:
 107                   - const: 1
 108                   - const: 2
 109                   - const: 3
 110                   - const: 4
 111
 112             required:
 113               - data-lanes
 114
 115     required:
 116       - port@0
 117       - port@1
 118
 119 required:
 120   - compatible
 121   - reg
 122   - interrupts
 123   - interrupt-names
 124   - clocks
 125   - clock-names
 126   - resets
 127   - reset-names
 128   - power-domains
 129   - ports
 130
 131 additionalProperties: false
 132
 133 examples:
 134   - |
 135     #include <dt-bindings/clock/r9a07g044-cpg.h>
 136     #include <dt-bindings/interrupt-controller/arm-gic.h>
 137
 138     dsi0: dsi@10850000 {
 139         compatible = "renesas,r9a07g044-mipi-dsi", "renesas,rzg2l-mipi-dsi";
 140         reg = <0x10850000 0x20000>;
 141         interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
 142                      <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
 143                      <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
 144                      <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
 145                      <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
 146                      <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
 147                      <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
 148         interrupt-names = "seq0", "seq1", "vin1", "rcv",
 149                           "ferr", "ppi", "debug";
 150         clocks = <&cpg CPG_MOD R9A07G044_MIPI_DSI_PLLCLK>,
 151                  <&cpg CPG_MOD R9A07G044_MIPI_DSI_SYSCLK>,
 152                  <&cpg CPG_MOD R9A07G044_MIPI_DSI_ACLK>,
 153                  <&cpg CPG_MOD R9A07G044_MIPI_DSI_PCLK>,
 154                  <&cpg CPG_MOD R9A07G044_MIPI_DSI_VCLK>,
 155                  <&cpg CPG_MOD R9A07G044_MIPI_DSI_LPCLK>;
 156         clock-names = "pllclk", "sysclk", "aclk", "pclk", "vclk", "lpclk";
 157         resets = <&cpg R9A07G044_MIPI_DSI_CMN_RSTB>,
 158                  <&cpg R9A07G044_MIPI_DSI_ARESET_N>,
 159                  <&cpg R9A07G044_MIPI_DSI_PRESET_N>;
 160         reset-names = "rst", "arst", "prst";
 161         power-domains = <&cpg>;
 162
 163         ports {
 164             #address-cells = <1>;
 165             #size-cells = <0>;
 166
 167             port@0 {
 168                 reg = <0>;
 169                 dsi0_in: endpoint {
 170                     remote-endpoint = <&du_out_dsi0>;
 171                 };
 172             };
 173
 174             port@1 {
 175                 reg = <1>;
 176                 dsi0_out: endpoint {
 177                     data-lanes = <1 2 3 4>;
 178                     remote-endpoint = <&adv7535_in>;
 179                 };
 180             };
 181         };
 182     };
 183 ...