bindings/display/bridge/nwl-dsi.yaml

   1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
   2 %YAML 1.2
   3 ---
   4 $id: http://devicetree.org/schemas/display/bridge/nwl-dsi.yaml#
   5 $schema: http://devicetree.org/meta-schemas/core.yaml#
   6
   7 title: Northwest Logic MIPI-DSI controller on i.MX SoCs
   8
   9 maintainers:
  10   - Guido Gúnther <agx@sigxcpu.org>
  11   - Robert Chiras <robert.chiras@nxp.com>
  12
  13 description: |
  14   NWL MIPI-DSI host controller found on i.MX8 platforms. This is a dsi bridge for
  15   the SOCs NWL MIPI-DSI host controller.
  16
  17 allOf:
  18   - $ref: ../dsi-controller.yaml#
  19
  20 properties:
  21   compatible:
  22     const: fsl,imx8mq-nwl-dsi
  23
  24   reg:
  25     maxItems: 1
  26
  27   interrupts:
  28     maxItems: 1
  29
  30   '#address-cells':
  31     const: 1
  32
  33   '#size-cells':
  34     const: 0
  35
  36   assigned-clock-parents: true
  37   assigned-clock-rates: true
  38   assigned-clocks: true
  39
  40   clocks:
  41     items:
  42       - description: DSI core clock
  43       - description: RX_ESC clock (used in escape mode)
  44       - description: TX_ESC clock (used in escape mode)
  45       - description: PHY_REF clock
  46       - description: LCDIF clock
  47
  48   clock-names:
  49     items:
  50       - const: core
  51       - const: rx_esc
  52       - const: tx_esc
  53       - const: phy_ref
  54       - const: lcdif
  55
  56   mux-controls:
  57     description:
  58       mux controller node to use for operating the input mux
  59
  60   phys:
  61     maxItems: 1
  62     description:
  63       A phandle to the phy module representing the DPHY
  64
  65   phy-names:
  66     items:
  67       - const: dphy
  68
  69   power-domains:
  70     maxItems: 1
  71
  72   resets:
  73     items:
  74       - description: dsi byte reset line
  75       - description: dsi dpi reset line
  76       - description: dsi esc reset line
  77       - description: dsi pclk reset line
  78
  79   reset-names:
  80     items:
  81       - const: byte
  82       - const: dpi
  83       - const: esc
  84       - const: pclk
  85
  86   ports:
  87     $ref: /schemas/graph.yaml#/properties/ports
  88
  89     properties:
  90       port@0:
  91         $ref: /schemas/graph.yaml#/$defs/port-base
  92         description:
  93           Input port node to receive pixel data from the
  94           display controller. Exactly one endpoint must be
  95           specified.
  96         properties:
  97           endpoint@0:
  98             $ref: /schemas/graph.yaml#/properties/endpoint
  99             description: sub-node describing the input from LCDIF
 100
 101           endpoint@1:
 102             $ref: /schemas/graph.yaml#/properties/endpoint
 103             description: sub-node describing the input from DCSS
 104
 105         oneOf:
 106           - required:
 107               - endpoint@0
 108           - required:
 109               - endpoint@1
 110
 111         unevaluatedProperties: false
 112
 113       port@1:
 114         $ref: /schemas/graph.yaml#/properties/port
 115         description:
 116           DSI output port node to the panel or the next bridge
 117           in the chain
 118
 119     required:
 120       - port@0
 121       - port@1
 122
 123 required:
 124   - '#address-cells'
 125   - '#size-cells'
 126   - clock-names
 127   - clocks
 128   - compatible
 129   - interrupts
 130   - mux-controls
 131   - phy-names
 132   - phys
 133   - ports
 134   - reg
 135   - reset-names
 136   - resets
 137
 138 unevaluatedProperties: false
 139
 140 examples:
 141   - |
 142     #include <dt-bindings/clock/imx8mq-clock.h>
 143     #include <dt-bindings/gpio/gpio.h>
 144     #include <dt-bindings/interrupt-controller/arm-gic.h>
 145     #include <dt-bindings/reset/imx8mq-reset.h>
 146
 147     dsi@30a00000 {
 148               #address-cells = <1>;
 149               #size-cells = <0>;
 150               compatible = "fsl,imx8mq-nwl-dsi";
 151               reg = <0x30A00000 0x300>;
 152               clocks = <&clk IMX8MQ_CLK_DSI_CORE>,
 153                        <&clk IMX8MQ_CLK_DSI_AHB>,
 154                        <&clk IMX8MQ_CLK_DSI_IPG_DIV>,
 155                        <&clk IMX8MQ_CLK_DSI_PHY_REF>,
 156                        <&clk IMX8MQ_CLK_LCDIF_PIXEL>;
 157               clock-names = "core", "rx_esc", "tx_esc", "phy_ref", "lcdif";
 158               interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 159               mux-controls = <&mux 0>;
 160               power-domains = <&pgc_mipi>;
 161               resets = <&src IMX8MQ_RESET_MIPI_DSI_RESET_BYTE_N>,
 162                        <&src IMX8MQ_RESET_MIPI_DSI_DPI_RESET_N>,
 163                        <&src IMX8MQ_RESET_MIPI_DSI_ESC_RESET_N>,
 164                        <&src IMX8MQ_RESET_MIPI_DSI_PCLK_RESET_N>;
 165               reset-names = "byte", "dpi", "esc", "pclk";
 166               phys = <&dphy>;
 167               phy-names = "dphy";
 168
 169               panel@0 {
 170                       compatible = "rocktech,jh057n00900";
 171                       reg = <0>;
 172                       vcc-supply = <&reg_2v8_p>;
 173                       iovcc-supply = <&reg_1v8_p>;
 174                       reset-gpios = <&gpio3 13 GPIO_ACTIVE_LOW>;
 175                       port {
 176                            panel_in: endpoint {
 177                                      remote-endpoint = <&mipi_dsi_out>;
 178                            };
 179                       };
 180               };
 181
 182               ports {
 183                     #address-cells = <1>;
 184                     #size-cells = <0>;
 185
 186                     port@0 {
 187                            #size-cells = <0>;
 188                            #address-cells = <1>;
 189                            reg = <0>;
 190                            mipi_dsi_in: endpoint@0 {
 191                                         reg = <0>;
 192                                         remote-endpoint = <&lcdif_mipi_dsi>;
 193                            };
 194                     };
 195                     port@1 {
 196                            reg = <1>;
 197                            mipi_dsi_out: endpoint {
 198                                          remote-endpoint = <&panel_in>;
 199                            };
 200                     };
 201               };
 202     };