1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/display/bridge/nwl-dsi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Northwest Logic MIPI-DSI controller on i.MX SoCs
10 - Guido GĂșnther <agx@sigxcpu.org>
11 - Robert Chiras <robert.chiras@nxp.com>
14 NWL MIPI-DSI host controller found on i.MX8 platforms. This is a dsi bridge for
15 the SOCs NWL MIPI-DSI host controller.
18 - $ref: ../dsi-controller.yaml#
22 const: fsl,imx8mq-nwl-dsi
36 assigned-clock-parents: true
37 assigned-clock-rates: true
42 - description: DSI core clock
43 - description: RX_ESC clock (used in escape mode)
44 - description: TX_ESC clock (used in escape mode)
45 - description: PHY_REF clock
46 - description: LCDIF clock
58 mux controller node to use for operating the input mux
63 A phandle to the phy module representing the DPHY
74 - description: dsi byte reset line
75 - description: dsi dpi reset line
76 - description: dsi esc reset line
77 - description: dsi pclk reset line
87 $ref: /schemas/graph.yaml#/properties/ports
91 $ref: /schemas/graph.yaml#/$defs/port-base
93 Input port node to receive pixel data from the
94 display controller. Exactly one endpoint must be
98 $ref: /schemas/graph.yaml#/properties/endpoint
99 description: sub-node describing the input from LCDIF
102 $ref: /schemas/graph.yaml#/properties/endpoint
103 description: sub-node describing the input from DCSS
111 unevaluatedProperties: false
114 $ref: /schemas/graph.yaml#/properties/port
116 DSI output port node to the panel or the next bridge
138 unevaluatedProperties: false
142 #include <dt-bindings/clock/imx8mq-clock.h>
143 #include <dt-bindings/gpio/gpio.h>
144 #include <dt-bindings/interrupt-controller/arm-gic.h>
145 #include <dt-bindings/reset/imx8mq-reset.h>
148 #address-cells = <1>;
150 compatible = "fsl,imx8mq-nwl-dsi";
151 reg = <0x30A00000 0x300>;
152 clocks = <&clk IMX8MQ_CLK_DSI_CORE>,
153 <&clk IMX8MQ_CLK_DSI_AHB>,
154 <&clk IMX8MQ_CLK_DSI_IPG_DIV>,
155 <&clk IMX8MQ_CLK_DSI_PHY_REF>,
156 <&clk IMX8MQ_CLK_LCDIF_PIXEL>;
157 clock-names = "core", "rx_esc", "tx_esc", "phy_ref", "lcdif";
158 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
159 mux-controls = <&mux 0>;
160 power-domains = <&pgc_mipi>;
161 resets = <&src IMX8MQ_RESET_MIPI_DSI_RESET_BYTE_N>,
162 <&src IMX8MQ_RESET_MIPI_DSI_DPI_RESET_N>,
163 <&src IMX8MQ_RESET_MIPI_DSI_ESC_RESET_N>,
164 <&src IMX8MQ_RESET_MIPI_DSI_PCLK_RESET_N>;
165 reset-names = "byte", "dpi", "esc", "pclk";
170 compatible = "rocktech,jh057n00900";
172 vcc-supply = <®_2v8_p>;
173 iovcc-supply = <®_1v8_p>;
174 reset-gpios = <&gpio3 13 GPIO_ACTIVE_LOW>;
177 remote-endpoint = <&mipi_dsi_out>;
183 #address-cells = <1>;
188 #address-cells = <1>;
190 mipi_dsi_in: endpoint@0 {
192 remote-endpoint = <&lcdif_mipi_dsi>;
197 mipi_dsi_out: endpoint {
198 remote-endpoint = <&panel_in>;