bindings/crypto/qcom-qce.yaml

   1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
   2 %YAML 1.2
   3 ---
   4 $id: http://devicetree.org/schemas/crypto/qcom-qce.yaml#
   5 $schema: http://devicetree.org/meta-schemas/core.yaml#
   6
   7 title: Qualcomm crypto engine driver
   8
   9 maintainers:
  10   - Bhupesh Sharma <bhupesh.sharma@linaro.org>
  11
  12 description:
  13   This document defines the binding for the QCE crypto
  14   controller found on Qualcomm parts.
  15
  16 properties:
  17   compatible:
  18     oneOf:
  19       - const: qcom,crypto-v5.1
  20         deprecated: true
  21         description: Kept only for ABI backward compatibility
  22
  23       - const: qcom,crypto-v5.4
  24         deprecated: true
  25         description: Kept only for ABI backward compatibility
  26
  27       - items:
  28           - enum:
  29               - qcom,ipq4019-qce
  30               - qcom,sm8150-qce
  31           - const: qcom,qce
  32
  33       - items:
  34           - enum:
  35               - qcom,ipq6018-qce
  36               - qcom,ipq8074-qce
  37               - qcom,ipq9574-qce
  38               - qcom,msm8996-qce
  39               - qcom,qcm2290-qce
  40               - qcom,sdm845-qce
  41               - qcom,sm6115-qce
  42           - const: qcom,ipq4019-qce
  43           - const: qcom,qce
  44
  45       - items:
  46           - enum:
  47               - qcom,sc7280-qce
  48               - qcom,sm8250-qce
  49               - qcom,sm8350-qce
  50               - qcom,sm8450-qce
  51               - qcom,sm8550-qce
  52               - qcom,sm8650-qce
  53           - const: qcom,sm8150-qce
  54           - const: qcom,qce
  55
  56   reg:
  57     maxItems: 1
  58
  59   clocks:
  60     minItems: 1
  61     maxItems: 3
  62
  63   clock-names:
  64     minItems: 1
  65     maxItems: 3
  66
  67   iommus:
  68     minItems: 1
  69     maxItems: 8
  70     description:
  71       phandle to apps_smmu node with sid mask.
  72
  73   interconnects:
  74     maxItems: 1
  75     description:
  76       Interconnect path between qce crypto and main memory.
  77
  78   interconnect-names:
  79     const: memory
  80
  81   dmas:
  82     items:
  83       - description: DMA specifiers for rx dma channel.
  84       - description: DMA specifiers for tx dma channel.
  85
  86   dma-names:
  87     items:
  88       - const: rx
  89       - const: tx
  90
  91 allOf:
  92   - if:
  93       properties:
  94         compatible:
  95           contains:
  96             enum:
  97               - qcom,crypto-v5.1
  98               - qcom,crypto-v5.4
  99               - qcom,ipq6018-qce
 100               - qcom,ipq8074-qce
 101               - qcom,ipq9574-qce
 102               - qcom,msm8996-qce
 103               - qcom,sdm845-qce
 104     then:
 105       properties:
 106         clocks:
 107           maxItems: 3
 108         clock-names:
 109           items:
 110             - const: iface
 111             - const: bus
 112             - const: core
 113       required:
 114         - clocks
 115         - clock-names
 116
 117   - if:
 118       properties:
 119         compatible:
 120           contains:
 121             enum:
 122               - qcom,qcm2290-qce
 123               - qcom,sm6115-qce
 124     then:
 125       properties:
 126         clocks:
 127           maxItems: 1
 128         clock-names:
 129           items:
 130             - const: core
 131       required:
 132         - clocks
 133         - clock-names
 134
 135   - if:
 136       properties:
 137         compatible:
 138           contains:
 139             enum:
 140               - qcom,sm8150-qce
 141     then:
 142       properties:
 143         clocks: false
 144         clock-names: false
 145
 146 required:
 147   - compatible
 148   - reg
 149   - dmas
 150   - dma-names
 151
 152 additionalProperties: false
 153
 154 examples:
 155   - |
 156     #include <dt-bindings/clock/qcom,gcc-apq8084.h>
 157     crypto-engine@fd45a000 {
 158         compatible = "qcom,ipq6018-qce", "qcom,ipq4019-qce", "qcom,qce";
 159         reg = <0xfd45a000 0x6000>;
 160         clocks = <&gcc GCC_CE2_AHB_CLK>,
 161                  <&gcc GCC_CE2_AXI_CLK>,
 162                  <&gcc GCC_CE2_CLK>;
 163         clock-names = "iface", "bus", "core";
 164         dmas = <&cryptobam 2>, <&cryptobam 3>;
 165         dma-names = "rx", "tx";
 166         iommus = <&apps_smmu 0x584 0x0011>,
 167                  <&apps_smmu 0x586 0x0011>,
 168                  <&apps_smmu 0x594 0x0011>,
 169                  <&apps_smmu 0x596 0x0011>;
 170     };