1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/ata/snps,dwc-ahci-common.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Synopsys DWC AHCI SATA controller properties
10 - Serge Semin <fancer.lancer@gmail.com>
13 This document defines device tree schema for the generic Synopsys DWC
14 AHCI controller properties.
19 - $ref: ahci-common.yaml#
30 Basic DWC AHCI SATA clock sources like application AXI/AHB BIU clock,
31 PM-alive clock, RxOOB detection clock, embedded PHYs reference (Rx/Tx)
41 - description: Application APB/AHB/AXI BIU clock
47 - description: Power Module keep-alive clock
49 - description: RxOOB detection clock
51 - description: PHY Transmit Clock
53 - description: PHY Receive Clock
55 - description: SATA Ports reference clock
60 At least basic application and reference clock domains resets are
61 normally supported by the DWC AHCI SATA controller.
70 - description: Application AHB/AXI BIU clock domain reset control
74 - description: Power Module keep-alive clock domain reset control
76 - description: RxOOB detection clock domain reset control
78 - description: Reference clock domain reset control
82 "^sata-port@[0-9a-e]$":
83 $ref: '#/$defs/dwc-ahci-port'
85 additionalProperties: true
89 $ref: /schemas/ata/ahci-common.yaml#/$defs/ahci-port
97 $ref: /schemas/types.yaml#/definitions/uint32
98 description: Maximal size of Tx DMA transactions in FIFO words
99 enum: [ 1, 2, 4, 8, 16, 32, 64, 128, 256, 512, 1024 ]
102 $ref: /schemas/types.yaml#/definitions/uint32
103 description: Maximal size of Rx DMA transactions in FIFO words
104 enum: [ 1, 2, 4, 8, 16, 32, 64, 128, 256, 512, 1024 ]