2 * Copyright 2017 Broadcom. All Rights Reserved.
3 * The term "Broadcom" refers to Broadcom Limited and/or its subsidiaries.
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License version 2
7 * as published by the Free Software Foundation. The full GNU General
8 * Public License is included in this distribution in the file called COPYING.
10 * Contact Information:
11 * linux-drivers@broadcom.com
15 #include <scsi/iscsi_proto.h>
21 /* UE Status Low CSR */
22 static const char * const desc_ue_status_low[] = {
57 /* UE Status High CSR */
58 static const char * const desc_ue_status_hi[] = {
93 struct be_mcc_wrb *alloc_mcc_wrb(struct beiscsi_hba *phba,
94 unsigned int *ref_tag)
96 struct be_queue_info *mccq = &phba->ctrl.mcc_obj.q;
97 struct be_mcc_wrb *wrb = NULL;
100 spin_lock(&phba->ctrl.mcc_lock);
101 if (mccq->used == mccq->len) {
102 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT |
103 BEISCSI_LOG_CONFIG | BEISCSI_LOG_MBOX,
104 "BC_%d : MCC queue full: WRB used %u tag avail %u\n",
105 mccq->used, phba->ctrl.mcc_tag_available);
109 if (!phba->ctrl.mcc_tag_available)
112 tag = phba->ctrl.mcc_tag[phba->ctrl.mcc_alloc_index];
114 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT |
115 BEISCSI_LOG_CONFIG | BEISCSI_LOG_MBOX,
116 "BC_%d : MCC tag 0 allocated: tag avail %u alloc index %u\n",
117 phba->ctrl.mcc_tag_available,
118 phba->ctrl.mcc_alloc_index);
122 /* return this tag for further reference */
124 phba->ctrl.mcc_tag[phba->ctrl.mcc_alloc_index] = 0;
125 phba->ctrl.mcc_tag_status[tag] = 0;
126 phba->ctrl.ptag_state[tag].tag_state = 0;
127 phba->ctrl.ptag_state[tag].cbfn = NULL;
128 phba->ctrl.mcc_tag_available--;
129 if (phba->ctrl.mcc_alloc_index == (MAX_MCC_CMD - 1))
130 phba->ctrl.mcc_alloc_index = 0;
132 phba->ctrl.mcc_alloc_index++;
134 wrb = queue_head_node(mccq);
135 memset(wrb, 0, sizeof(*wrb));
137 wrb->tag0 |= (mccq->head << MCC_Q_WRB_IDX_SHIFT) & MCC_Q_WRB_IDX_MASK;
138 queue_head_inc(mccq);
142 spin_unlock(&phba->ctrl.mcc_lock);
146 void free_mcc_wrb(struct be_ctrl_info *ctrl, unsigned int tag)
148 struct be_queue_info *mccq = &ctrl->mcc_obj.q;
150 spin_lock(&ctrl->mcc_lock);
151 tag = tag & MCC_Q_CMD_TAG_MASK;
152 ctrl->mcc_tag[ctrl->mcc_free_index] = tag;
153 if (ctrl->mcc_free_index == (MAX_MCC_CMD - 1))
154 ctrl->mcc_free_index = 0;
156 ctrl->mcc_free_index++;
157 ctrl->mcc_tag_available++;
159 spin_unlock(&ctrl->mcc_lock);
163 * beiscsi_mcc_compl_status - Return the status of MCC completion
164 * @phba: Driver private structure
165 * @tag: Tag for the MBX Command
166 * @wrb: the WRB used for the MBX Command
167 * @mbx_cmd_mem: ptr to memory allocated for MBX Cmd
173 int __beiscsi_mcc_compl_status(struct beiscsi_hba *phba,
175 struct be_mcc_wrb **wrb,
176 struct be_dma_mem *mbx_cmd_mem)
178 struct be_queue_info *mccq = &phba->ctrl.mcc_obj.q;
179 uint16_t status = 0, addl_status = 0, wrb_num = 0;
180 struct be_cmd_resp_hdr *mbx_resp_hdr;
181 struct be_cmd_req_hdr *mbx_hdr;
182 struct be_mcc_wrb *temp_wrb;
183 uint32_t mcc_tag_status;
186 mcc_tag_status = phba->ctrl.mcc_tag_status[tag];
187 status = (mcc_tag_status & CQE_STATUS_MASK);
188 addl_status = ((mcc_tag_status & CQE_STATUS_ADDL_MASK) >>
189 CQE_STATUS_ADDL_SHIFT);
192 mbx_hdr = (struct be_cmd_req_hdr *)mbx_cmd_mem->va;
194 wrb_num = (mcc_tag_status & CQE_STATUS_WRB_MASK) >>
195 CQE_STATUS_WRB_SHIFT;
196 temp_wrb = (struct be_mcc_wrb *)queue_get_wrb(mccq, wrb_num);
197 mbx_hdr = embedded_payload(temp_wrb);
203 if (status || addl_status) {
204 beiscsi_log(phba, KERN_WARNING,
205 BEISCSI_LOG_INIT | BEISCSI_LOG_EH |
207 "BC_%d : MBX Cmd Failed for Subsys : %d Opcode : %d with Status : %d and Extd_Status : %d\n",
208 mbx_hdr->subsystem, mbx_hdr->opcode,
209 status, addl_status);
211 if (status == MCC_STATUS_INSUFFICIENT_BUFFER) {
212 mbx_resp_hdr = (struct be_cmd_resp_hdr *)mbx_hdr;
213 beiscsi_log(phba, KERN_WARNING,
214 BEISCSI_LOG_INIT | BEISCSI_LOG_EH |
216 "BC_%d : Insufficient Buffer Error Resp_Len : %d Actual_Resp_Len : %d\n",
217 mbx_resp_hdr->response_length,
218 mbx_resp_hdr->actual_resp_len);
227 * beiscsi_mccq_compl_wait()- Process completion in MCC CQ
228 * @phba: Driver private structure
229 * @tag: Tag for the MBX Command
230 * @wrb: the WRB used for the MBX Command
231 * @mbx_cmd_mem: ptr to memory allocated for MBX Cmd
233 * Waits for MBX completion with the passed TAG.
239 int beiscsi_mccq_compl_wait(struct beiscsi_hba *phba,
241 struct be_mcc_wrb **wrb,
242 struct be_dma_mem *mbx_cmd_mem)
246 if (!tag || tag > MAX_MCC_CMD) {
247 __beiscsi_log(phba, KERN_ERR,
248 "BC_%d : invalid tag %u\n", tag);
252 if (beiscsi_hba_in_error(phba)) {
253 clear_bit(MCC_TAG_STATE_RUNNING,
254 &phba->ctrl.ptag_state[tag].tag_state);
258 /* wait for the mccq completion */
259 rc = wait_event_interruptible_timeout(phba->ctrl.mcc_wait[tag],
260 phba->ctrl.mcc_tag_status[tag],
262 BEISCSI_HOST_MBX_TIMEOUT));
264 * Return EIO if port is being disabled. Associated DMA memory, if any,
265 * is freed by the caller. When port goes offline, MCCQ is cleaned up
268 if (!test_bit(BEISCSI_HBA_ONLINE, &phba->state)) {
269 clear_bit(MCC_TAG_STATE_RUNNING,
270 &phba->ctrl.ptag_state[tag].tag_state);
275 * If MBOX cmd timeout expired, tag and resource allocated
276 * for cmd is not freed until FW returns completion.
279 struct be_dma_mem *tag_mem;
282 * PCI/DMA memory allocated and posted in non-embedded mode
283 * will have mbx_cmd_mem != NULL.
284 * Save virtual and bus addresses for the command so that it
285 * can be freed later.
287 tag_mem = &phba->ctrl.ptag_state[tag].tag_mem_state;
289 tag_mem->size = mbx_cmd_mem->size;
290 tag_mem->va = mbx_cmd_mem->va;
291 tag_mem->dma = mbx_cmd_mem->dma;
295 /* first make tag_mem_state visible to all */
297 set_bit(MCC_TAG_STATE_TIMEOUT,
298 &phba->ctrl.ptag_state[tag].tag_state);
300 beiscsi_log(phba, KERN_ERR,
301 BEISCSI_LOG_INIT | BEISCSI_LOG_EH |
303 "BC_%d : MBX Cmd Completion timed out\n");
307 rc = __beiscsi_mcc_compl_status(phba, tag, wrb, mbx_cmd_mem);
309 free_mcc_wrb(&phba->ctrl, tag);
314 * beiscsi_process_mbox_compl()- Check the MBX completion status
315 * @ctrl: Function specific MBX data structure
316 * @compl: Completion status of MBX Command
318 * Check for the MBX completion status when BMBX method used
324 static int beiscsi_process_mbox_compl(struct be_ctrl_info *ctrl,
325 struct be_mcc_compl *compl)
327 struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem);
328 struct beiscsi_hba *phba = pci_get_drvdata(ctrl->pdev);
329 struct be_cmd_req_hdr *hdr = embedded_payload(wrb);
330 u16 compl_status, extd_status;
333 * To check if valid bit is set, check the entire word as we don't know
334 * the endianness of the data (old entry is host endian while a new
335 * entry is little endian)
338 beiscsi_log(phba, KERN_ERR,
339 BEISCSI_LOG_CONFIG | BEISCSI_LOG_MBOX,
340 "BC_%d : BMBX busy, no completion\n");
343 compl->flags = le32_to_cpu(compl->flags);
344 WARN_ON((compl->flags & CQE_FLAGS_VALID_MASK) == 0);
347 * Just swap the status to host endian;
348 * mcc tag is opaquely copied from mcc_wrb.
350 be_dws_le_to_cpu(compl, 4);
351 compl_status = (compl->status >> CQE_STATUS_COMPL_SHIFT) &
352 CQE_STATUS_COMPL_MASK;
353 extd_status = (compl->status >> CQE_STATUS_EXTD_SHIFT) &
354 CQE_STATUS_EXTD_MASK;
355 /* Need to reset the entire word that houses the valid bit */
358 if (compl_status == MCC_STATUS_SUCCESS)
361 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_CONFIG | BEISCSI_LOG_MBOX,
362 "BC_%d : error in cmd completion: Subsystem : %d Opcode : %d status(compl/extd)=%d/%d\n",
363 hdr->subsystem, hdr->opcode, compl_status, extd_status);
367 static void beiscsi_process_async_link(struct beiscsi_hba *phba,
368 struct be_mcc_compl *compl)
370 struct be_async_event_link_state *evt;
372 evt = (struct be_async_event_link_state *)compl;
374 phba->port_speed = evt->port_speed;
376 * Check logical link status in ASYNC event.
377 * This has been newly introduced in SKH-R Firmware 10.0.338.45.
379 if (evt->port_link_status & BE_ASYNC_LINK_UP_MASK) {
380 set_bit(BEISCSI_HBA_LINK_UP, &phba->state);
381 if (test_bit(BEISCSI_HBA_BOOT_FOUND, &phba->state))
382 beiscsi_start_boot_work(phba, BE_BOOT_INVALID_SHANDLE);
383 __beiscsi_log(phba, KERN_ERR,
384 "BC_%d : Link Up on Port %d tag 0x%x\n",
385 evt->physical_port, evt->event_tag);
387 clear_bit(BEISCSI_HBA_LINK_UP, &phba->state);
388 __beiscsi_log(phba, KERN_ERR,
389 "BC_%d : Link Down on Port %d tag 0x%x\n",
390 evt->physical_port, evt->event_tag);
391 iscsi_host_for_each_session(phba->shost,
392 beiscsi_session_fail);
396 static char *beiscsi_port_misconf_event_msg[] = {
397 "Physical Link is functional.",
398 "Optics faulted/incorrectly installed/not installed - Reseat optics, if issue not resolved, replace.",
399 "Optics of two types installed - Remove one optic or install matching pair of optics.",
400 "Incompatible optics - Replace with compatible optics for card to function.",
401 "Unqualified optics - Replace with Avago optics for Warranty and Technical Support.",
402 "Uncertified optics - Replace with Avago Certified optics to enable link operation."
405 static void beiscsi_process_async_sli(struct beiscsi_hba *phba,
406 struct be_mcc_compl *compl)
408 struct be_async_event_sli *async_sli;
409 u8 evt_type, state, old_state, le;
410 char *sev = KERN_WARNING;
413 evt_type = compl->flags >> ASYNC_TRAILER_EVENT_TYPE_SHIFT;
414 evt_type &= ASYNC_TRAILER_EVENT_TYPE_MASK;
416 /* processing only MISCONFIGURED physical port event */
417 if (evt_type != ASYNC_SLI_EVENT_TYPE_MISCONFIGURED)
420 async_sli = (struct be_async_event_sli *)compl;
421 state = async_sli->event_data1 >>
422 (phba->fw_config.phys_port * 8) & 0xff;
423 le = async_sli->event_data2 >>
424 (phba->fw_config.phys_port * 8) & 0xff;
426 old_state = phba->optic_state;
427 phba->optic_state = state;
429 if (state >= ARRAY_SIZE(beiscsi_port_misconf_event_msg)) {
430 /* fw is reporting a state we don't know, log and return */
431 __beiscsi_log(phba, KERN_ERR,
432 "BC_%d : Port %c: Unrecognized optic state 0x%x\n",
433 phba->port_name, async_sli->event_data1);
437 if (ASYNC_SLI_LINK_EFFECT_VALID(le)) {
438 /* log link effect for unqualified-4, uncertified-5 optics */
440 msg = (ASYNC_SLI_LINK_EFFECT_STATE(le)) ?
441 " Link is non-operational." :
442 " Link is operational.";
444 if (ASYNC_SLI_LINK_EFFECT_SEV(le) == 1)
447 if (ASYNC_SLI_LINK_EFFECT_SEV(le) == 2)
451 if (old_state != phba->optic_state)
452 __beiscsi_log(phba, sev, "BC_%d : Port %c: %s%s\n",
454 beiscsi_port_misconf_event_msg[state],
458 void beiscsi_process_async_event(struct beiscsi_hba *phba,
459 struct be_mcc_compl *compl)
461 char *sev = KERN_INFO;
464 /* interpret flags as an async trailer */
465 evt_code = compl->flags >> ASYNC_TRAILER_EVENT_CODE_SHIFT;
466 evt_code &= ASYNC_TRAILER_EVENT_CODE_MASK;
468 case ASYNC_EVENT_CODE_LINK_STATE:
469 beiscsi_process_async_link(phba, compl);
471 case ASYNC_EVENT_CODE_ISCSI:
472 if (test_bit(BEISCSI_HBA_BOOT_FOUND, &phba->state))
473 beiscsi_start_boot_work(phba, BE_BOOT_INVALID_SHANDLE);
476 case ASYNC_EVENT_CODE_SLI:
477 beiscsi_process_async_sli(phba, compl);
480 /* event not registered */
484 beiscsi_log(phba, sev, BEISCSI_LOG_CONFIG | BEISCSI_LOG_MBOX,
485 "BC_%d : ASYNC Event %x: status 0x%08x flags 0x%08x\n",
486 evt_code, compl->status, compl->flags);
489 int beiscsi_process_mcc_compl(struct be_ctrl_info *ctrl,
490 struct be_mcc_compl *compl)
492 struct beiscsi_hba *phba = pci_get_drvdata(ctrl->pdev);
493 u16 compl_status, extd_status;
494 struct be_dma_mem *tag_mem;
495 unsigned int tag, wrb_idx;
497 be_dws_le_to_cpu(compl, 4);
498 tag = (compl->tag0 & MCC_Q_CMD_TAG_MASK);
499 wrb_idx = (compl->tag0 & CQE_STATUS_WRB_MASK) >> CQE_STATUS_WRB_SHIFT;
501 if (!test_bit(MCC_TAG_STATE_RUNNING,
502 &ctrl->ptag_state[tag].tag_state)) {
503 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_MBOX |
504 BEISCSI_LOG_INIT | BEISCSI_LOG_CONFIG,
505 "BC_%d : MBX cmd completed but not posted\n");
509 /* end MCC with this tag */
510 clear_bit(MCC_TAG_STATE_RUNNING, &ctrl->ptag_state[tag].tag_state);
512 if (test_bit(MCC_TAG_STATE_TIMEOUT, &ctrl->ptag_state[tag].tag_state)) {
513 beiscsi_log(phba, KERN_WARNING,
514 BEISCSI_LOG_MBOX | BEISCSI_LOG_INIT |
516 "BC_%d : MBX Completion for timeout Command from FW\n");
518 * Check for the size before freeing resource.
519 * Only for non-embedded cmd, PCI resource is allocated.
521 tag_mem = &ctrl->ptag_state[tag].tag_mem_state;
523 pci_free_consistent(ctrl->pdev, tag_mem->size,
524 tag_mem->va, tag_mem->dma);
527 free_mcc_wrb(ctrl, tag);
531 compl_status = (compl->status >> CQE_STATUS_COMPL_SHIFT) &
532 CQE_STATUS_COMPL_MASK;
533 extd_status = (compl->status >> CQE_STATUS_EXTD_SHIFT) &
534 CQE_STATUS_EXTD_MASK;
535 /* The ctrl.mcc_tag_status[tag] is filled with
536 * [31] = valid, [30:24] = Rsvd, [23:16] = wrb, [15:8] = extd_status,
537 * [7:0] = compl_status
539 ctrl->mcc_tag_status[tag] = CQE_VALID_MASK;
540 ctrl->mcc_tag_status[tag] |= (wrb_idx << CQE_STATUS_WRB_SHIFT);
541 ctrl->mcc_tag_status[tag] |= (extd_status << CQE_STATUS_ADDL_SHIFT) &
542 CQE_STATUS_ADDL_MASK;
543 ctrl->mcc_tag_status[tag] |= (compl_status & CQE_STATUS_MASK);
545 if (test_bit(MCC_TAG_STATE_ASYNC, &ctrl->ptag_state[tag].tag_state)) {
546 if (ctrl->ptag_state[tag].cbfn)
547 ctrl->ptag_state[tag].cbfn(phba, tag);
549 __beiscsi_log(phba, KERN_ERR,
550 "BC_%d : MBX ASYNC command with no callback\n");
551 free_mcc_wrb(ctrl, tag);
555 if (test_bit(MCC_TAG_STATE_IGNORE, &ctrl->ptag_state[tag].tag_state)) {
556 /* just check completion status and free wrb */
557 __beiscsi_mcc_compl_status(phba, tag, NULL, NULL);
558 free_mcc_wrb(ctrl, tag);
562 wake_up_interruptible(&ctrl->mcc_wait[tag]);
566 void be_mcc_notify(struct beiscsi_hba *phba, unsigned int tag)
568 struct be_queue_info *mccq = &phba->ctrl.mcc_obj.q;
571 set_bit(MCC_TAG_STATE_RUNNING, &phba->ctrl.ptag_state[tag].tag_state);
572 val |= mccq->id & DB_MCCQ_RING_ID_MASK;
573 val |= 1 << DB_MCCQ_NUM_POSTED_SHIFT;
574 /* make request available for DMA */
576 iowrite32(val, phba->db_va + DB_MCCQ_OFFSET);
580 * be_mbox_db_ready_poll()- Check ready status
581 * @ctrl: Function specific MBX data structure
583 * Check for the ready status of FW to send BMBX
584 * commands to adapter.
590 static int be_mbox_db_ready_poll(struct be_ctrl_info *ctrl)
592 /* wait 30s for generic non-flash MBOX operation */
593 #define BEISCSI_MBX_RDY_BIT_TIMEOUT 30000
594 void __iomem *db = ctrl->db + MPU_MAILBOX_DB_OFFSET;
595 struct beiscsi_hba *phba = pci_get_drvdata(ctrl->pdev);
596 unsigned long timeout;
600 * This BMBX busy wait path is used during init only.
601 * For the commands executed during init, 5s should suffice.
603 timeout = jiffies + msecs_to_jiffies(BEISCSI_MBX_RDY_BIT_TIMEOUT);
605 if (beiscsi_hba_in_error(phba))
608 ready = ioread32(db);
609 if (ready == 0xffffffff)
612 ready &= MPU_MAILBOX_DB_RDY_MASK;
616 if (time_after(jiffies, timeout))
618 /* 1ms sleep is enough in most cases */
619 schedule_timeout_uninterruptible(msecs_to_jiffies(1));
622 beiscsi_log(phba, KERN_ERR,
623 BEISCSI_LOG_CONFIG | BEISCSI_LOG_MBOX,
624 "BC_%d : FW Timed Out\n");
625 set_bit(BEISCSI_HBA_FW_TIMEOUT, &phba->state);
630 * be_mbox_notify: Notify adapter of new BMBX command
631 * @ctrl: Function specific MBX data structure
633 * Ring doorbell to inform adapter of a BMBX command
640 static int be_mbox_notify(struct be_ctrl_info *ctrl)
644 void __iomem *db = ctrl->db + MPU_MAILBOX_DB_OFFSET;
645 struct be_dma_mem *mbox_mem = &ctrl->mbox_mem;
646 struct be_mcc_mailbox *mbox = mbox_mem->va;
648 status = be_mbox_db_ready_poll(ctrl);
652 val &= ~MPU_MAILBOX_DB_RDY_MASK;
653 val |= MPU_MAILBOX_DB_HI_MASK;
654 val |= (upper_32_bits(mbox_mem->dma) >> 2) << 2;
657 status = be_mbox_db_ready_poll(ctrl);
662 val &= ~MPU_MAILBOX_DB_RDY_MASK;
663 val &= ~MPU_MAILBOX_DB_HI_MASK;
664 val |= (u32) (mbox_mem->dma >> 4) << 2;
667 status = be_mbox_db_ready_poll(ctrl);
671 /* RDY is set; small delay before CQE read. */
674 status = beiscsi_process_mbox_compl(ctrl, &mbox->compl);
678 void be_wrb_hdr_prepare(struct be_mcc_wrb *wrb, u32 payload_len,
679 bool embedded, u8 sge_cnt)
682 wrb->emb_sgecnt_special |= MCC_WRB_EMBEDDED_MASK;
684 wrb->emb_sgecnt_special |= (sge_cnt & MCC_WRB_SGE_CNT_MASK) <<
685 MCC_WRB_SGE_CNT_SHIFT;
686 wrb->payload_length = payload_len;
687 be_dws_cpu_to_le(wrb, 8);
690 void be_cmd_hdr_prepare(struct be_cmd_req_hdr *req_hdr,
691 u8 subsystem, u8 opcode, u32 cmd_len)
693 req_hdr->opcode = opcode;
694 req_hdr->subsystem = subsystem;
695 req_hdr->request_length = cpu_to_le32(cmd_len - sizeof(*req_hdr));
696 req_hdr->timeout = BEISCSI_FW_MBX_TIMEOUT;
699 static void be_cmd_page_addrs_prepare(struct phys_addr *pages, u32 max_pages,
700 struct be_dma_mem *mem)
703 u64 dma = (u64) mem->dma;
705 buf_pages = min(PAGES_4K_SPANNED(mem->va, mem->size), max_pages);
706 for (i = 0; i < buf_pages; i++) {
707 pages[i].lo = cpu_to_le32(dma & 0xFFFFFFFF);
708 pages[i].hi = cpu_to_le32(upper_32_bits(dma));
713 static u32 eq_delay_to_mult(u32 usec_delay)
715 #define MAX_INTR_RATE 651042
716 const u32 round = 10;
722 u32 interrupt_rate = 1000000 / usec_delay;
723 if (interrupt_rate == 0)
726 multiplier = (MAX_INTR_RATE - interrupt_rate) * round;
727 multiplier /= interrupt_rate;
728 multiplier = (multiplier + round / 2) / round;
729 multiplier = min(multiplier, (u32) 1023);
735 struct be_mcc_wrb *wrb_from_mbox(struct be_dma_mem *mbox_mem)
737 return &((struct be_mcc_mailbox *)(mbox_mem->va))->wrb;
740 int beiscsi_cmd_eq_create(struct be_ctrl_info *ctrl,
741 struct be_queue_info *eq, int eq_delay)
743 struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem);
744 struct be_cmd_req_eq_create *req = embedded_payload(wrb);
745 struct be_cmd_resp_eq_create *resp = embedded_payload(wrb);
746 struct be_dma_mem *q_mem = &eq->dma_mem;
749 mutex_lock(&ctrl->mbox_lock);
750 memset(wrb, 0, sizeof(*wrb));
752 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0);
754 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
755 OPCODE_COMMON_EQ_CREATE, sizeof(*req));
757 req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
759 AMAP_SET_BITS(struct amap_eq_context, func, req->context,
760 PCI_FUNC(ctrl->pdev->devfn));
761 AMAP_SET_BITS(struct amap_eq_context, valid, req->context, 1);
762 AMAP_SET_BITS(struct amap_eq_context, size, req->context, 0);
763 AMAP_SET_BITS(struct amap_eq_context, count, req->context,
764 __ilog2_u32(eq->len / 256));
765 AMAP_SET_BITS(struct amap_eq_context, delaymult, req->context,
766 eq_delay_to_mult(eq_delay));
767 be_dws_cpu_to_le(req->context, sizeof(req->context));
769 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
771 status = be_mbox_notify(ctrl);
773 eq->id = le16_to_cpu(resp->eq_id);
776 mutex_unlock(&ctrl->mbox_lock);
780 int beiscsi_cmd_cq_create(struct be_ctrl_info *ctrl,
781 struct be_queue_info *cq, struct be_queue_info *eq,
782 bool sol_evts, bool no_delay, int coalesce_wm)
784 struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem);
785 struct be_cmd_req_cq_create *req = embedded_payload(wrb);
786 struct be_cmd_resp_cq_create *resp = embedded_payload(wrb);
787 struct beiscsi_hba *phba = pci_get_drvdata(ctrl->pdev);
788 struct be_dma_mem *q_mem = &cq->dma_mem;
789 void *ctxt = &req->context;
792 mutex_lock(&ctrl->mbox_lock);
793 memset(wrb, 0, sizeof(*wrb));
795 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0);
797 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
798 OPCODE_COMMON_CQ_CREATE, sizeof(*req));
800 req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
801 if (is_chip_be2_be3r(phba)) {
802 AMAP_SET_BITS(struct amap_cq_context, coalescwm,
804 AMAP_SET_BITS(struct amap_cq_context, nodelay, ctxt, no_delay);
805 AMAP_SET_BITS(struct amap_cq_context, count, ctxt,
806 __ilog2_u32(cq->len / 256));
807 AMAP_SET_BITS(struct amap_cq_context, valid, ctxt, 1);
808 AMAP_SET_BITS(struct amap_cq_context, solevent, ctxt, sol_evts);
809 AMAP_SET_BITS(struct amap_cq_context, eventable, ctxt, 1);
810 AMAP_SET_BITS(struct amap_cq_context, eqid, ctxt, eq->id);
811 AMAP_SET_BITS(struct amap_cq_context, armed, ctxt, 1);
812 AMAP_SET_BITS(struct amap_cq_context, func, ctxt,
813 PCI_FUNC(ctrl->pdev->devfn));
815 req->hdr.version = MBX_CMD_VER2;
817 AMAP_SET_BITS(struct amap_cq_context_v2, coalescwm,
819 AMAP_SET_BITS(struct amap_cq_context_v2, nodelay,
821 AMAP_SET_BITS(struct amap_cq_context_v2, count, ctxt,
822 __ilog2_u32(cq->len / 256));
823 AMAP_SET_BITS(struct amap_cq_context_v2, valid, ctxt, 1);
824 AMAP_SET_BITS(struct amap_cq_context_v2, eventable, ctxt, 1);
825 AMAP_SET_BITS(struct amap_cq_context_v2, eqid, ctxt, eq->id);
826 AMAP_SET_BITS(struct amap_cq_context_v2, armed, ctxt, 1);
829 be_dws_cpu_to_le(ctxt, sizeof(req->context));
831 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
833 status = be_mbox_notify(ctrl);
835 cq->id = le16_to_cpu(resp->cq_id);
838 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
839 "BC_%d : In be_cmd_cq_create, status=ox%08x\n",
842 mutex_unlock(&ctrl->mbox_lock);
847 static u32 be_encoded_q_len(int q_len)
849 u32 len_encoded = fls(q_len); /* log2(len) + 1 */
850 if (len_encoded == 16)
855 int beiscsi_cmd_mccq_create(struct beiscsi_hba *phba,
856 struct be_queue_info *mccq,
857 struct be_queue_info *cq)
859 struct be_mcc_wrb *wrb;
860 struct be_cmd_req_mcc_create_ext *req;
861 struct be_dma_mem *q_mem = &mccq->dma_mem;
862 struct be_ctrl_info *ctrl;
866 mutex_lock(&phba->ctrl.mbox_lock);
868 wrb = wrb_from_mbox(&ctrl->mbox_mem);
869 memset(wrb, 0, sizeof(*wrb));
870 req = embedded_payload(wrb);
871 ctxt = &req->context;
873 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0);
875 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
876 OPCODE_COMMON_MCC_CREATE_EXT, sizeof(*req));
878 req->num_pages = PAGES_4K_SPANNED(q_mem->va, q_mem->size);
879 req->async_evt_bitmap = 1 << ASYNC_EVENT_CODE_LINK_STATE;
880 req->async_evt_bitmap |= 1 << ASYNC_EVENT_CODE_ISCSI;
881 req->async_evt_bitmap |= 1 << ASYNC_EVENT_CODE_SLI;
883 AMAP_SET_BITS(struct amap_mcc_context, fid, ctxt,
884 PCI_FUNC(phba->pcidev->devfn));
885 AMAP_SET_BITS(struct amap_mcc_context, valid, ctxt, 1);
886 AMAP_SET_BITS(struct amap_mcc_context, ring_size, ctxt,
887 be_encoded_q_len(mccq->len));
888 AMAP_SET_BITS(struct amap_mcc_context, cq_id, ctxt, cq->id);
890 be_dws_cpu_to_le(ctxt, sizeof(req->context));
892 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
894 status = be_mbox_notify(ctrl);
896 struct be_cmd_resp_mcc_create *resp = embedded_payload(wrb);
897 mccq->id = le16_to_cpu(resp->id);
898 mccq->created = true;
900 mutex_unlock(&phba->ctrl.mbox_lock);
905 int beiscsi_cmd_q_destroy(struct be_ctrl_info *ctrl, struct be_queue_info *q,
908 struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem);
909 struct be_cmd_req_q_destroy *req = embedded_payload(wrb);
910 struct beiscsi_hba *phba = pci_get_drvdata(ctrl->pdev);
911 u8 subsys = 0, opcode = 0;
914 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
915 "BC_%d : In beiscsi_cmd_q_destroy "
916 "queue_type : %d\n", queue_type);
918 mutex_lock(&ctrl->mbox_lock);
919 memset(wrb, 0, sizeof(*wrb));
920 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0);
922 switch (queue_type) {
924 subsys = CMD_SUBSYSTEM_COMMON;
925 opcode = OPCODE_COMMON_EQ_DESTROY;
928 subsys = CMD_SUBSYSTEM_COMMON;
929 opcode = OPCODE_COMMON_CQ_DESTROY;
932 subsys = CMD_SUBSYSTEM_COMMON;
933 opcode = OPCODE_COMMON_MCC_DESTROY;
936 subsys = CMD_SUBSYSTEM_ISCSI;
937 opcode = OPCODE_COMMON_ISCSI_WRBQ_DESTROY;
940 subsys = CMD_SUBSYSTEM_ISCSI;
941 opcode = OPCODE_COMMON_ISCSI_DEFQ_DESTROY;
944 subsys = CMD_SUBSYSTEM_ISCSI;
945 opcode = OPCODE_COMMON_ISCSI_CFG_REMOVE_SGL_PAGES;
948 mutex_unlock(&ctrl->mbox_lock);
951 be_cmd_hdr_prepare(&req->hdr, subsys, opcode, sizeof(*req));
952 if (queue_type != QTYPE_SGL)
953 req->id = cpu_to_le16(q->id);
955 status = be_mbox_notify(ctrl);
957 mutex_unlock(&ctrl->mbox_lock);
962 * be_cmd_create_default_pdu_queue()- Create DEFQ for the adapter
963 * @ctrl: ptr to ctrl_info
964 * @cq: Completion Queue
967 * @entry_size: size of each entry in DEFQ
968 * @is_header: Header or Data DEFQ
969 * @ulp_num: Bind to which ULP
971 * Create HDR/Data DEFQ for the passed ULP. Unsol PDU are posted
972 * on this queue by the FW
976 * Failure: Non-Zero Value
979 int be_cmd_create_default_pdu_queue(struct be_ctrl_info *ctrl,
980 struct be_queue_info *cq,
981 struct be_queue_info *dq, int length,
982 int entry_size, uint8_t is_header,
985 struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem);
986 struct be_defq_create_req *req = embedded_payload(wrb);
987 struct be_dma_mem *q_mem = &dq->dma_mem;
988 struct beiscsi_hba *phba = pci_get_drvdata(ctrl->pdev);
989 void *ctxt = &req->context;
992 mutex_lock(&ctrl->mbox_lock);
993 memset(wrb, 0, sizeof(*wrb));
995 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0);
997 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ISCSI,
998 OPCODE_COMMON_ISCSI_DEFQ_CREATE, sizeof(*req));
1000 req->num_pages = PAGES_4K_SPANNED(q_mem->va, q_mem->size);
1001 if (phba->fw_config.dual_ulp_aware) {
1002 req->ulp_num = ulp_num;
1003 req->dua_feature |= (1 << BEISCSI_DUAL_ULP_AWARE_BIT);
1004 req->dua_feature |= (1 << BEISCSI_BIND_Q_TO_ULP_BIT);
1007 if (is_chip_be2_be3r(phba)) {
1008 AMAP_SET_BITS(struct amap_be_default_pdu_context,
1010 AMAP_SET_BITS(struct amap_be_default_pdu_context,
1011 rx_pdid_valid, ctxt, 1);
1012 AMAP_SET_BITS(struct amap_be_default_pdu_context,
1013 pci_func_id, ctxt, PCI_FUNC(ctrl->pdev->devfn));
1014 AMAP_SET_BITS(struct amap_be_default_pdu_context,
1016 be_encoded_q_len(length /
1017 sizeof(struct phys_addr)));
1018 AMAP_SET_BITS(struct amap_be_default_pdu_context,
1019 default_buffer_size, ctxt, entry_size);
1020 AMAP_SET_BITS(struct amap_be_default_pdu_context,
1021 cq_id_recv, ctxt, cq->id);
1023 AMAP_SET_BITS(struct amap_default_pdu_context_ext,
1025 AMAP_SET_BITS(struct amap_default_pdu_context_ext,
1026 rx_pdid_valid, ctxt, 1);
1027 AMAP_SET_BITS(struct amap_default_pdu_context_ext,
1029 be_encoded_q_len(length /
1030 sizeof(struct phys_addr)));
1031 AMAP_SET_BITS(struct amap_default_pdu_context_ext,
1032 default_buffer_size, ctxt, entry_size);
1033 AMAP_SET_BITS(struct amap_default_pdu_context_ext,
1034 cq_id_recv, ctxt, cq->id);
1037 be_dws_cpu_to_le(ctxt, sizeof(req->context));
1039 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
1041 status = be_mbox_notify(ctrl);
1043 struct be_ring *defq_ring;
1044 struct be_defq_create_resp *resp = embedded_payload(wrb);
1046 dq->id = le16_to_cpu(resp->id);
1049 defq_ring = &phba->phwi_ctrlr->default_pdu_hdr[ulp_num];
1051 defq_ring = &phba->phwi_ctrlr->
1052 default_pdu_data[ulp_num];
1054 defq_ring->id = dq->id;
1056 if (!phba->fw_config.dual_ulp_aware) {
1057 defq_ring->ulp_num = BEISCSI_ULP0;
1058 defq_ring->doorbell_offset = DB_RXULP0_OFFSET;
1060 defq_ring->ulp_num = resp->ulp_num;
1061 defq_ring->doorbell_offset = resp->doorbell_offset;
1064 mutex_unlock(&ctrl->mbox_lock);
1070 * be_cmd_wrbq_create()- Create WRBQ
1071 * @ctrl: ptr to ctrl_info
1072 * @q_mem: memory details for the queue
1074 * @pwrb_context: ptr to wrb_context
1075 * @ulp_num: ULP on which the WRBQ is to be created
1077 * Create WRBQ on the passed ULP_NUM.
1080 int be_cmd_wrbq_create(struct be_ctrl_info *ctrl,
1081 struct be_dma_mem *q_mem,
1082 struct be_queue_info *wrbq,
1083 struct hwi_wrb_context *pwrb_context,
1086 struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem);
1087 struct be_wrbq_create_req *req = embedded_payload(wrb);
1088 struct be_wrbq_create_resp *resp = embedded_payload(wrb);
1089 struct beiscsi_hba *phba = pci_get_drvdata(ctrl->pdev);
1092 mutex_lock(&ctrl->mbox_lock);
1093 memset(wrb, 0, sizeof(*wrb));
1095 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0);
1097 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ISCSI,
1098 OPCODE_COMMON_ISCSI_WRBQ_CREATE, sizeof(*req));
1099 req->num_pages = PAGES_4K_SPANNED(q_mem->va, q_mem->size);
1101 if (phba->fw_config.dual_ulp_aware) {
1102 req->ulp_num = ulp_num;
1103 req->dua_feature |= (1 << BEISCSI_DUAL_ULP_AWARE_BIT);
1104 req->dua_feature |= (1 << BEISCSI_BIND_Q_TO_ULP_BIT);
1107 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
1109 status = be_mbox_notify(ctrl);
1111 wrbq->id = le16_to_cpu(resp->cid);
1112 wrbq->created = true;
1114 pwrb_context->cid = wrbq->id;
1115 if (!phba->fw_config.dual_ulp_aware) {
1116 pwrb_context->doorbell_offset = DB_TXULP0_OFFSET;
1117 pwrb_context->ulp_num = BEISCSI_ULP0;
1119 pwrb_context->ulp_num = resp->ulp_num;
1120 pwrb_context->doorbell_offset = resp->doorbell_offset;
1123 mutex_unlock(&ctrl->mbox_lock);
1127 int be_cmd_iscsi_post_template_hdr(struct be_ctrl_info *ctrl,
1128 struct be_dma_mem *q_mem)
1130 struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem);
1131 struct be_post_template_pages_req *req = embedded_payload(wrb);
1134 mutex_lock(&ctrl->mbox_lock);
1136 memset(wrb, 0, sizeof(*wrb));
1137 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0);
1138 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1139 OPCODE_COMMON_ADD_TEMPLATE_HEADER_BUFFERS,
1142 req->num_pages = PAGES_4K_SPANNED(q_mem->va, q_mem->size);
1143 req->type = BEISCSI_TEMPLATE_HDR_TYPE_ISCSI;
1144 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
1146 status = be_mbox_notify(ctrl);
1147 mutex_unlock(&ctrl->mbox_lock);
1151 int be_cmd_iscsi_remove_template_hdr(struct be_ctrl_info *ctrl)
1153 struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem);
1154 struct be_remove_template_pages_req *req = embedded_payload(wrb);
1157 mutex_lock(&ctrl->mbox_lock);
1159 memset(wrb, 0, sizeof(*wrb));
1160 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0);
1161 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1162 OPCODE_COMMON_REMOVE_TEMPLATE_HEADER_BUFFERS,
1165 req->type = BEISCSI_TEMPLATE_HDR_TYPE_ISCSI;
1167 status = be_mbox_notify(ctrl);
1168 mutex_unlock(&ctrl->mbox_lock);
1172 int be_cmd_iscsi_post_sgl_pages(struct be_ctrl_info *ctrl,
1173 struct be_dma_mem *q_mem,
1174 u32 page_offset, u32 num_pages)
1176 struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem);
1177 struct be_post_sgl_pages_req *req = embedded_payload(wrb);
1178 struct beiscsi_hba *phba = pci_get_drvdata(ctrl->pdev);
1180 unsigned int curr_pages;
1181 u32 internal_page_offset = 0;
1182 u32 temp_num_pages = num_pages;
1184 if (num_pages == 0xff)
1187 mutex_lock(&ctrl->mbox_lock);
1189 memset(wrb, 0, sizeof(*wrb));
1190 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0);
1191 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ISCSI,
1192 OPCODE_COMMON_ISCSI_CFG_POST_SGL_PAGES,
1194 curr_pages = BE_NUMBER_OF_FIELD(struct be_post_sgl_pages_req,
1196 req->num_pages = min(num_pages, curr_pages);
1197 req->page_offset = page_offset;
1198 be_cmd_page_addrs_prepare(req->pages, req->num_pages, q_mem);
1199 q_mem->dma = q_mem->dma + (req->num_pages * PAGE_SIZE);
1200 internal_page_offset += req->num_pages;
1201 page_offset += req->num_pages;
1202 num_pages -= req->num_pages;
1204 if (temp_num_pages == 0xff)
1205 req->num_pages = temp_num_pages;
1207 status = be_mbox_notify(ctrl);
1209 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
1210 "BC_%d : FW CMD to map iscsi frags failed.\n");
1214 } while (num_pages > 0);
1216 mutex_unlock(&ctrl->mbox_lock);
1218 beiscsi_cmd_q_destroy(ctrl, NULL, QTYPE_SGL);
1223 * be_cmd_set_vlan()- Configure VLAN paramters on the adapter
1224 * @phba: device priv structure instance
1225 * @vlan_tag: TAG to be set
1227 * Set the VLAN_TAG for the adapter or Disable VLAN on adapter
1230 * TAG for the MBX Cmd
1232 int be_cmd_set_vlan(struct beiscsi_hba *phba,
1236 struct be_mcc_wrb *wrb;
1237 struct be_cmd_set_vlan_req *req;
1238 struct be_ctrl_info *ctrl = &phba->ctrl;
1240 if (mutex_lock_interruptible(&ctrl->mbox_lock))
1242 wrb = alloc_mcc_wrb(phba, &tag);
1244 mutex_unlock(&ctrl->mbox_lock);
1248 req = embedded_payload(wrb);
1249 be_wrb_hdr_prepare(wrb, sizeof(*wrb), true, 0);
1250 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ISCSI,
1251 OPCODE_COMMON_ISCSI_NTWK_SET_VLAN,
1254 req->interface_hndl = phba->interface_handle;
1255 req->vlan_priority = vlan_tag;
1257 be_mcc_notify(phba, tag);
1258 mutex_unlock(&ctrl->mbox_lock);
1263 int beiscsi_check_supported_fw(struct be_ctrl_info *ctrl,
1264 struct beiscsi_hba *phba)
1266 struct be_dma_mem nonemb_cmd;
1267 struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem);
1268 struct be_mgmt_controller_attributes *req;
1269 struct be_sge *sge = nonembedded_sgl(wrb);
1272 nonemb_cmd.va = pci_alloc_consistent(ctrl->pdev,
1273 sizeof(struct be_mgmt_controller_attributes),
1275 if (nonemb_cmd.va == NULL) {
1276 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
1277 "BG_%d : pci_alloc_consistent failed in %s\n",
1281 nonemb_cmd.size = sizeof(struct be_mgmt_controller_attributes);
1282 req = nonemb_cmd.va;
1283 memset(req, 0, sizeof(*req));
1284 mutex_lock(&ctrl->mbox_lock);
1285 memset(wrb, 0, sizeof(*wrb));
1286 be_wrb_hdr_prepare(wrb, sizeof(*req), false, 1);
1287 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1288 OPCODE_COMMON_GET_CNTL_ATTRIBUTES, sizeof(*req));
1289 sge->pa_hi = cpu_to_le32(upper_32_bits(nonemb_cmd.dma));
1290 sge->pa_lo = cpu_to_le32(nonemb_cmd.dma & 0xFFFFFFFF);
1291 sge->len = cpu_to_le32(nonemb_cmd.size);
1292 status = be_mbox_notify(ctrl);
1294 struct be_mgmt_controller_attributes_resp *resp = nonemb_cmd.va;
1296 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
1297 "BG_%d : Firmware Version of CMD : %s\n"
1298 "Firmware Version is : %s\n"
1299 "Developer Build, not performing version check...\n",
1300 resp->params.hba_attribs
1301 .flashrom_version_string,
1302 resp->params.hba_attribs.
1303 firmware_version_string);
1305 phba->fw_config.iscsi_features =
1306 resp->params.hba_attribs.iscsi_features;
1307 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
1308 "BM_%d : phba->fw_config.iscsi_features = %d\n",
1309 phba->fw_config.iscsi_features);
1310 memcpy(phba->fw_ver_str, resp->params.hba_attribs.
1311 firmware_version_string, BEISCSI_VER_STRLEN);
1313 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
1314 "BG_%d : Failed in beiscsi_check_supported_fw\n");
1315 mutex_unlock(&ctrl->mbox_lock);
1317 pci_free_consistent(ctrl->pdev, nonemb_cmd.size,
1318 nonemb_cmd.va, nonemb_cmd.dma);
1324 * beiscsi_get_fw_config()- Get the FW config for the function
1325 * @ctrl: ptr to Ctrl Info
1326 * @phba: ptr to the dev priv structure
1328 * Get the FW config and resources available for the function.
1329 * The resources are created based on the count received here.
1333 * Failure: Non-Zero Value
1335 int beiscsi_get_fw_config(struct be_ctrl_info *ctrl,
1336 struct beiscsi_hba *phba)
1338 struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem);
1339 struct be_fw_cfg *pfw_cfg = embedded_payload(wrb);
1340 uint32_t cid_count, icd_count;
1341 int status = -EINVAL;
1342 uint8_t ulp_num = 0;
1344 mutex_lock(&ctrl->mbox_lock);
1345 memset(wrb, 0, sizeof(*wrb));
1346 be_wrb_hdr_prepare(wrb, sizeof(*pfw_cfg), true, 0);
1348 be_cmd_hdr_prepare(&pfw_cfg->hdr, CMD_SUBSYSTEM_COMMON,
1349 OPCODE_COMMON_QUERY_FIRMWARE_CONFIG,
1350 EMBED_MBX_MAX_PAYLOAD_SIZE);
1352 if (be_mbox_notify(ctrl)) {
1353 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
1354 "BG_%d : Failed in beiscsi_get_fw_config\n");
1358 /* FW response formats depend on port id */
1359 phba->fw_config.phys_port = pfw_cfg->phys_port;
1360 if (phba->fw_config.phys_port >= BEISCSI_PHYS_PORT_MAX) {
1361 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
1362 "BG_%d : invalid physical port id %d\n",
1363 phba->fw_config.phys_port);
1367 /* populate and check FW config against min and max values */
1368 if (!is_chip_be2_be3r(phba)) {
1369 phba->fw_config.eqid_count = pfw_cfg->eqid_count;
1370 phba->fw_config.cqid_count = pfw_cfg->cqid_count;
1371 if (phba->fw_config.eqid_count == 0 ||
1372 phba->fw_config.eqid_count > 2048) {
1373 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
1374 "BG_%d : invalid EQ count %d\n",
1375 phba->fw_config.eqid_count);
1378 if (phba->fw_config.cqid_count == 0 ||
1379 phba->fw_config.cqid_count > 4096) {
1380 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
1381 "BG_%d : invalid CQ count %d\n",
1382 phba->fw_config.cqid_count);
1385 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
1386 "BG_%d : EQ_Count : %d CQ_Count : %d\n",
1387 phba->fw_config.eqid_count,
1388 phba->fw_config.cqid_count);
1392 * Check on which all ULP iSCSI Protocol is loaded.
1393 * Set the Bit for those ULP. This set flag is used
1394 * at all places in the code to check on which ULP
1395 * iSCSi Protocol is loaded
1397 for (ulp_num = 0; ulp_num < BEISCSI_ULP_COUNT; ulp_num++) {
1398 if (pfw_cfg->ulp[ulp_num].ulp_mode &
1399 BEISCSI_ULP_ISCSI_INI_MODE) {
1400 set_bit(ulp_num, &phba->fw_config.ulp_supported);
1402 /* Get the CID, ICD and Chain count for each ULP */
1403 phba->fw_config.iscsi_cid_start[ulp_num] =
1404 pfw_cfg->ulp[ulp_num].sq_base;
1405 phba->fw_config.iscsi_cid_count[ulp_num] =
1406 pfw_cfg->ulp[ulp_num].sq_count;
1408 phba->fw_config.iscsi_icd_start[ulp_num] =
1409 pfw_cfg->ulp[ulp_num].icd_base;
1410 phba->fw_config.iscsi_icd_count[ulp_num] =
1411 pfw_cfg->ulp[ulp_num].icd_count;
1413 phba->fw_config.iscsi_chain_start[ulp_num] =
1414 pfw_cfg->chain_icd[ulp_num].chain_base;
1415 phba->fw_config.iscsi_chain_count[ulp_num] =
1416 pfw_cfg->chain_icd[ulp_num].chain_count;
1418 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
1419 "BG_%d : Function loaded on ULP : %d\n"
1420 "\tiscsi_cid_count : %d\n"
1421 "\tiscsi_cid_start : %d\n"
1422 "\t iscsi_icd_count : %d\n"
1423 "\t iscsi_icd_start : %d\n",
1426 iscsi_cid_count[ulp_num],
1428 iscsi_cid_start[ulp_num],
1430 iscsi_icd_count[ulp_num],
1432 iscsi_icd_start[ulp_num]);
1436 if (phba->fw_config.ulp_supported == 0) {
1437 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
1438 "BG_%d : iSCSI initiator mode not set: ULP0 %x ULP1 %x\n",
1439 pfw_cfg->ulp[BEISCSI_ULP0].ulp_mode,
1440 pfw_cfg->ulp[BEISCSI_ULP1].ulp_mode);
1445 * ICD is shared among ULPs. Use icd_count of any one loaded ULP
1447 for (ulp_num = 0; ulp_num < BEISCSI_ULP_COUNT; ulp_num++)
1448 if (test_bit(ulp_num, &phba->fw_config.ulp_supported))
1450 icd_count = phba->fw_config.iscsi_icd_count[ulp_num];
1451 if (icd_count == 0 || icd_count > 65536) {
1452 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
1453 "BG_%d: invalid ICD count %d\n", icd_count);
1457 cid_count = BEISCSI_GET_CID_COUNT(phba, BEISCSI_ULP0) +
1458 BEISCSI_GET_CID_COUNT(phba, BEISCSI_ULP1);
1459 if (cid_count == 0 || cid_count > 4096) {
1460 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
1461 "BG_%d: invalid CID count %d\n", cid_count);
1466 * Check FW is dual ULP aware i.e. can handle either
1469 phba->fw_config.dual_ulp_aware = (pfw_cfg->function_mode &
1470 BEISCSI_FUNC_DUA_MODE);
1472 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
1473 "BG_%d : DUA Mode : 0x%x\n",
1474 phba->fw_config.dual_ulp_aware);
1476 /* all set, continue using this FW config */
1479 mutex_unlock(&ctrl->mbox_lock);
1484 * beiscsi_get_port_name()- Get port name for the function
1485 * @ctrl: ptr to Ctrl Info
1486 * @phba: ptr to the dev priv structure
1488 * Get the alphanumeric character for port
1491 int beiscsi_get_port_name(struct be_ctrl_info *ctrl, struct beiscsi_hba *phba)
1494 struct be_mcc_wrb *wrb;
1495 struct be_cmd_get_port_name *ioctl;
1497 mutex_lock(&ctrl->mbox_lock);
1498 wrb = wrb_from_mbox(&ctrl->mbox_mem);
1499 memset(wrb, 0, sizeof(*wrb));
1500 ioctl = embedded_payload(wrb);
1502 be_wrb_hdr_prepare(wrb, sizeof(*ioctl), true, 0);
1503 be_cmd_hdr_prepare(&ioctl->h.req_hdr, CMD_SUBSYSTEM_COMMON,
1504 OPCODE_COMMON_GET_PORT_NAME,
1505 EMBED_MBX_MAX_PAYLOAD_SIZE);
1506 ret = be_mbox_notify(ctrl);
1507 phba->port_name = 0;
1509 phba->port_name = ioctl->p.resp.port_names >>
1510 (phba->fw_config.phys_port * 8) & 0xff;
1512 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
1513 "BG_%d : GET_PORT_NAME ret 0x%x status 0x%x\n",
1514 ret, ioctl->h.resp_hdr.status);
1517 if (phba->port_name == 0)
1518 phba->port_name = '?';
1520 mutex_unlock(&ctrl->mbox_lock);
1524 int beiscsi_set_host_data(struct beiscsi_hba *phba)
1526 struct be_ctrl_info *ctrl = &phba->ctrl;
1527 struct be_cmd_set_host_data *ioctl;
1528 struct be_mcc_wrb *wrb;
1531 if (is_chip_be2_be3r(phba))
1534 mutex_lock(&ctrl->mbox_lock);
1535 wrb = wrb_from_mbox(&ctrl->mbox_mem);
1536 memset(wrb, 0, sizeof(*wrb));
1537 ioctl = embedded_payload(wrb);
1539 be_wrb_hdr_prepare(wrb, sizeof(*ioctl), true, 0);
1540 be_cmd_hdr_prepare(&ioctl->h.req_hdr, CMD_SUBSYSTEM_COMMON,
1541 OPCODE_COMMON_SET_HOST_DATA,
1542 EMBED_MBX_MAX_PAYLOAD_SIZE);
1543 ioctl->param.req.param_id = BE_CMD_SET_HOST_PARAM_ID;
1544 ioctl->param.req.param_len =
1545 snprintf((char *)ioctl->param.req.param_data,
1546 sizeof(ioctl->param.req.param_data),
1547 "Linux iSCSI v%s", BUILD_STR);
1548 ioctl->param.req.param_len = ALIGN(ioctl->param.req.param_len + 1, 4);
1549 if (ioctl->param.req.param_len > BE_CMD_MAX_DRV_VERSION)
1550 ioctl->param.req.param_len = BE_CMD_MAX_DRV_VERSION;
1551 ret = be_mbox_notify(ctrl);
1553 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
1554 "BG_%d : HBA set host driver version\n");
1557 * Check "MCC_STATUS_INVALID_LENGTH" for SKH.
1558 * Older FW versions return this error.
1560 if (ret == MCC_STATUS_ILLEGAL_REQUEST ||
1561 ret == MCC_STATUS_INVALID_LENGTH)
1562 __beiscsi_log(phba, KERN_INFO,
1563 "BG_%d : HBA failed to set host driver version\n");
1566 mutex_unlock(&ctrl->mbox_lock);
1570 int beiscsi_set_uer_feature(struct beiscsi_hba *phba)
1572 struct be_ctrl_info *ctrl = &phba->ctrl;
1573 struct be_cmd_set_features *ioctl;
1574 struct be_mcc_wrb *wrb;
1577 mutex_lock(&ctrl->mbox_lock);
1578 wrb = wrb_from_mbox(&ctrl->mbox_mem);
1579 memset(wrb, 0, sizeof(*wrb));
1580 ioctl = embedded_payload(wrb);
1582 be_wrb_hdr_prepare(wrb, sizeof(*ioctl), true, 0);
1583 be_cmd_hdr_prepare(&ioctl->h.req_hdr, CMD_SUBSYSTEM_COMMON,
1584 OPCODE_COMMON_SET_FEATURES,
1585 EMBED_MBX_MAX_PAYLOAD_SIZE);
1586 ioctl->feature = BE_CMD_SET_FEATURE_UER;
1587 ioctl->param_len = sizeof(ioctl->param.req);
1588 ioctl->param.req.uer = BE_CMD_UER_SUPP_BIT;
1589 ret = be_mbox_notify(ctrl);
1591 phba->ue2rp = ioctl->param.resp.ue2rp;
1592 set_bit(BEISCSI_HBA_UER_SUPP, &phba->state);
1593 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
1594 "BG_%d : HBA error recovery supported\n");
1597 * Check "MCC_STATUS_INVALID_LENGTH" for SKH.
1598 * Older FW versions return this error.
1600 if (ret == MCC_STATUS_ILLEGAL_REQUEST ||
1601 ret == MCC_STATUS_INVALID_LENGTH)
1602 __beiscsi_log(phba, KERN_INFO,
1603 "BG_%d : HBA error recovery not supported\n");
1606 mutex_unlock(&ctrl->mbox_lock);
1610 static u32 beiscsi_get_post_stage(struct beiscsi_hba *phba)
1614 if (is_chip_be2_be3r(phba))
1615 sem = ioread32(phba->csr_va + SLIPORT_SEMAPHORE_OFFSET_BEx);
1617 pci_read_config_dword(phba->pcidev,
1618 SLIPORT_SEMAPHORE_OFFSET_SH, &sem);
1622 int beiscsi_check_fw_rdy(struct beiscsi_hba *phba)
1624 u32 loop, post, rdy = 0;
1628 post = beiscsi_get_post_stage(phba);
1629 if (post & POST_ERROR_BIT)
1631 if ((post & POST_STAGE_MASK) == POST_STAGE_ARMFW_RDY) {
1639 __beiscsi_log(phba, KERN_ERR,
1640 "BC_%d : FW not ready 0x%x\n", post);
1646 int beiscsi_cmd_function_reset(struct beiscsi_hba *phba)
1648 struct be_ctrl_info *ctrl = &phba->ctrl;
1649 struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem);
1650 struct be_post_sgl_pages_req *req;
1653 mutex_lock(&ctrl->mbox_lock);
1655 req = embedded_payload(wrb);
1656 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0);
1657 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1658 OPCODE_COMMON_FUNCTION_RESET, sizeof(*req));
1659 status = be_mbox_notify(ctrl);
1661 mutex_unlock(&ctrl->mbox_lock);
1665 int beiscsi_cmd_special_wrb(struct be_ctrl_info *ctrl, u32 load)
1667 struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem);
1668 struct beiscsi_hba *phba = pci_get_drvdata(ctrl->pdev);
1672 mutex_lock(&ctrl->mbox_lock);
1673 memset(wrb, 0, sizeof(*wrb));
1675 endian_check = (u8 *) wrb;
1677 /* to start communicating */
1678 *endian_check++ = 0xFF;
1679 *endian_check++ = 0x12;
1680 *endian_check++ = 0x34;
1681 *endian_check++ = 0xFF;
1682 *endian_check++ = 0xFF;
1683 *endian_check++ = 0x56;
1684 *endian_check++ = 0x78;
1685 *endian_check++ = 0xFF;
1687 /* to stop communicating */
1688 *endian_check++ = 0xFF;
1689 *endian_check++ = 0xAA;
1690 *endian_check++ = 0xBB;
1691 *endian_check++ = 0xFF;
1692 *endian_check++ = 0xFF;
1693 *endian_check++ = 0xCC;
1694 *endian_check++ = 0xDD;
1695 *endian_check = 0xFF;
1697 be_dws_cpu_to_le(wrb, sizeof(*wrb));
1699 status = be_mbox_notify(ctrl);
1701 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
1702 "BC_%d : special WRB message failed\n");
1703 mutex_unlock(&ctrl->mbox_lock);
1707 int beiscsi_init_sliport(struct beiscsi_hba *phba)
1711 /* check POST stage before talking to FW */
1712 status = beiscsi_check_fw_rdy(phba);
1716 /* clear all error states after checking FW rdy */
1717 phba->state &= ~BEISCSI_HBA_IN_ERR;
1719 /* check again UER support */
1720 phba->state &= ~BEISCSI_HBA_UER_SUPP;
1723 * SLI COMMON_FUNCTION_RESET completion is indicated by BMBX RDY bit.
1724 * It should clean up any stale info in FW for this fn.
1726 status = beiscsi_cmd_function_reset(phba);
1728 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
1729 "BC_%d : SLI Function Reset failed\n");
1733 /* indicate driver is loading */
1734 return beiscsi_cmd_special_wrb(&phba->ctrl, 1);
1738 * beiscsi_cmd_iscsi_cleanup()- Inform FW to cleanup EP data structures.
1739 * @phba: pointer to dev priv structure
1744 * Failure: Non-Zero Value
1746 int beiscsi_cmd_iscsi_cleanup(struct beiscsi_hba *phba, unsigned short ulp)
1748 struct be_ctrl_info *ctrl = &phba->ctrl;
1749 struct iscsi_cleanup_req_v1 *req_v1;
1750 struct iscsi_cleanup_req *req;
1751 u16 hdr_ring_id, data_ring_id;
1752 struct be_mcc_wrb *wrb;
1755 mutex_lock(&ctrl->mbox_lock);
1756 wrb = wrb_from_mbox(&ctrl->mbox_mem);
1758 hdr_ring_id = HWI_GET_DEF_HDRQ_ID(phba, ulp);
1759 data_ring_id = HWI_GET_DEF_BUFQ_ID(phba, ulp);
1760 if (is_chip_be2_be3r(phba)) {
1761 req = embedded_payload(wrb);
1762 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0);
1763 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ISCSI,
1764 OPCODE_COMMON_ISCSI_CLEANUP, sizeof(*req));
1765 req->chute = (1 << ulp);
1766 /* BE2/BE3 FW creates 8-bit ring id */
1767 req->hdr_ring_id = hdr_ring_id;
1768 req->data_ring_id = data_ring_id;
1770 req_v1 = embedded_payload(wrb);
1771 be_wrb_hdr_prepare(wrb, sizeof(*req_v1), true, 0);
1772 be_cmd_hdr_prepare(&req_v1->hdr, CMD_SUBSYSTEM_ISCSI,
1773 OPCODE_COMMON_ISCSI_CLEANUP,
1775 req_v1->hdr.version = 1;
1776 req_v1->chute = (1 << ulp);
1777 req_v1->hdr_ring_id = cpu_to_le16(hdr_ring_id);
1778 req_v1->data_ring_id = cpu_to_le16(data_ring_id);
1781 status = be_mbox_notify(ctrl);
1783 beiscsi_log(phba, KERN_WARNING, BEISCSI_LOG_INIT,
1784 "BG_%d : %s failed %d\n", __func__, ulp);
1785 mutex_unlock(&ctrl->mbox_lock);
1790 * beiscsi_detect_ue()- Detect Unrecoverable Error on adapter
1791 * @phba: Driver priv structure
1793 * Read registers linked to UE and check for the UE status
1795 int beiscsi_detect_ue(struct beiscsi_hba *phba)
1797 uint32_t ue_mask_hi = 0, ue_mask_lo = 0;
1798 uint32_t ue_hi = 0, ue_lo = 0;
1802 pci_read_config_dword(phba->pcidev,
1803 PCICFG_UE_STATUS_LOW, &ue_lo);
1804 pci_read_config_dword(phba->pcidev,
1805 PCICFG_UE_STATUS_MASK_LOW,
1807 pci_read_config_dword(phba->pcidev,
1808 PCICFG_UE_STATUS_HIGH,
1810 pci_read_config_dword(phba->pcidev,
1811 PCICFG_UE_STATUS_MASK_HI,
1814 ue_lo = (ue_lo & ~ue_mask_lo);
1815 ue_hi = (ue_hi & ~ue_mask_hi);
1818 if (ue_lo || ue_hi) {
1819 set_bit(BEISCSI_HBA_IN_UE, &phba->state);
1820 __beiscsi_log(phba, KERN_ERR,
1821 "BC_%d : HBA error detected\n");
1826 for (i = 0; ue_lo; ue_lo >>= 1, i++) {
1828 __beiscsi_log(phba, KERN_ERR,
1829 "BC_%d : UE_LOW %s bit set\n",
1830 desc_ue_status_low[i]);
1835 for (i = 0; ue_hi; ue_hi >>= 1, i++) {
1837 __beiscsi_log(phba, KERN_ERR,
1838 "BC_%d : UE_HIGH %s bit set\n",
1839 desc_ue_status_hi[i]);
1846 * beiscsi_detect_tpe()- Detect Transient Parity Error on adapter
1847 * @phba: Driver priv structure
1849 * Read SLIPORT SEMAPHORE register to check for UER
1852 int beiscsi_detect_tpe(struct beiscsi_hba *phba)
1857 post = beiscsi_get_post_stage(phba);
1858 status = post & POST_STAGE_MASK;
1859 if ((status & POST_ERR_RECOVERY_CODE_MASK) ==
1860 POST_STAGE_RECOVERABLE_ERR) {
1861 set_bit(BEISCSI_HBA_IN_TPE, &phba->state);
1862 __beiscsi_log(phba, KERN_INFO,
1863 "BC_%d : HBA error recoverable: 0x%x\n", post);
1866 __beiscsi_log(phba, KERN_INFO,
1867 "BC_%d : HBA in UE: 0x%x\n", post);