2 * B53 switch driver main logic
4 * Copyright (C) 2011-2013 Jonas Gorski <jogo@openwrt.org>
5 * Copyright (C) 2016 Florian Fainelli <f.fainelli@gmail.com>
7 * Permission to use, copy, modify, and/or distribute this software for any
8 * purpose with or without fee is hereby granted, provided that the above
9 * copyright notice and this permission notice appear in all copies.
11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
20 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
22 #include <linux/delay.h>
23 #include <linux/export.h>
24 #include <linux/gpio.h>
25 #include <linux/kernel.h>
26 #include <linux/module.h>
27 #include <linux/platform_data/b53.h>
28 #include <linux/phy.h>
29 #include <linux/etherdevice.h>
30 #include <linux/if_bridge.h>
32 #include <net/switchdev.h>
43 /* BCM5365 MIB counters */
44 static const struct b53_mib_desc b53_mibs_65[] = {
45 { 8, 0x00, "TxOctets" },
46 { 4, 0x08, "TxDropPkts" },
47 { 4, 0x10, "TxBroadcastPkts" },
48 { 4, 0x14, "TxMulticastPkts" },
49 { 4, 0x18, "TxUnicastPkts" },
50 { 4, 0x1c, "TxCollisions" },
51 { 4, 0x20, "TxSingleCollision" },
52 { 4, 0x24, "TxMultipleCollision" },
53 { 4, 0x28, "TxDeferredTransmit" },
54 { 4, 0x2c, "TxLateCollision" },
55 { 4, 0x30, "TxExcessiveCollision" },
56 { 4, 0x38, "TxPausePkts" },
57 { 8, 0x44, "RxOctets" },
58 { 4, 0x4c, "RxUndersizePkts" },
59 { 4, 0x50, "RxPausePkts" },
60 { 4, 0x54, "Pkts64Octets" },
61 { 4, 0x58, "Pkts65to127Octets" },
62 { 4, 0x5c, "Pkts128to255Octets" },
63 { 4, 0x60, "Pkts256to511Octets" },
64 { 4, 0x64, "Pkts512to1023Octets" },
65 { 4, 0x68, "Pkts1024to1522Octets" },
66 { 4, 0x6c, "RxOversizePkts" },
67 { 4, 0x70, "RxJabbers" },
68 { 4, 0x74, "RxAlignmentErrors" },
69 { 4, 0x78, "RxFCSErrors" },
70 { 8, 0x7c, "RxGoodOctets" },
71 { 4, 0x84, "RxDropPkts" },
72 { 4, 0x88, "RxUnicastPkts" },
73 { 4, 0x8c, "RxMulticastPkts" },
74 { 4, 0x90, "RxBroadcastPkts" },
75 { 4, 0x94, "RxSAChanges" },
76 { 4, 0x98, "RxFragments" },
79 #define B53_MIBS_65_SIZE ARRAY_SIZE(b53_mibs_65)
81 /* BCM63xx MIB counters */
82 static const struct b53_mib_desc b53_mibs_63xx[] = {
83 { 8, 0x00, "TxOctets" },
84 { 4, 0x08, "TxDropPkts" },
85 { 4, 0x0c, "TxQoSPkts" },
86 { 4, 0x10, "TxBroadcastPkts" },
87 { 4, 0x14, "TxMulticastPkts" },
88 { 4, 0x18, "TxUnicastPkts" },
89 { 4, 0x1c, "TxCollisions" },
90 { 4, 0x20, "TxSingleCollision" },
91 { 4, 0x24, "TxMultipleCollision" },
92 { 4, 0x28, "TxDeferredTransmit" },
93 { 4, 0x2c, "TxLateCollision" },
94 { 4, 0x30, "TxExcessiveCollision" },
95 { 4, 0x38, "TxPausePkts" },
96 { 8, 0x3c, "TxQoSOctets" },
97 { 8, 0x44, "RxOctets" },
98 { 4, 0x4c, "RxUndersizePkts" },
99 { 4, 0x50, "RxPausePkts" },
100 { 4, 0x54, "Pkts64Octets" },
101 { 4, 0x58, "Pkts65to127Octets" },
102 { 4, 0x5c, "Pkts128to255Octets" },
103 { 4, 0x60, "Pkts256to511Octets" },
104 { 4, 0x64, "Pkts512to1023Octets" },
105 { 4, 0x68, "Pkts1024to1522Octets" },
106 { 4, 0x6c, "RxOversizePkts" },
107 { 4, 0x70, "RxJabbers" },
108 { 4, 0x74, "RxAlignmentErrors" },
109 { 4, 0x78, "RxFCSErrors" },
110 { 8, 0x7c, "RxGoodOctets" },
111 { 4, 0x84, "RxDropPkts" },
112 { 4, 0x88, "RxUnicastPkts" },
113 { 4, 0x8c, "RxMulticastPkts" },
114 { 4, 0x90, "RxBroadcastPkts" },
115 { 4, 0x94, "RxSAChanges" },
116 { 4, 0x98, "RxFragments" },
117 { 4, 0xa0, "RxSymbolErrors" },
118 { 4, 0xa4, "RxQoSPkts" },
119 { 8, 0xa8, "RxQoSOctets" },
120 { 4, 0xb0, "Pkts1523to2047Octets" },
121 { 4, 0xb4, "Pkts2048to4095Octets" },
122 { 4, 0xb8, "Pkts4096to8191Octets" },
123 { 4, 0xbc, "Pkts8192to9728Octets" },
124 { 4, 0xc0, "RxDiscarded" },
127 #define B53_MIBS_63XX_SIZE ARRAY_SIZE(b53_mibs_63xx)
130 static const struct b53_mib_desc b53_mibs[] = {
131 { 8, 0x00, "TxOctets" },
132 { 4, 0x08, "TxDropPkts" },
133 { 4, 0x10, "TxBroadcastPkts" },
134 { 4, 0x14, "TxMulticastPkts" },
135 { 4, 0x18, "TxUnicastPkts" },
136 { 4, 0x1c, "TxCollisions" },
137 { 4, 0x20, "TxSingleCollision" },
138 { 4, 0x24, "TxMultipleCollision" },
139 { 4, 0x28, "TxDeferredTransmit" },
140 { 4, 0x2c, "TxLateCollision" },
141 { 4, 0x30, "TxExcessiveCollision" },
142 { 4, 0x38, "TxPausePkts" },
143 { 8, 0x50, "RxOctets" },
144 { 4, 0x58, "RxUndersizePkts" },
145 { 4, 0x5c, "RxPausePkts" },
146 { 4, 0x60, "Pkts64Octets" },
147 { 4, 0x64, "Pkts65to127Octets" },
148 { 4, 0x68, "Pkts128to255Octets" },
149 { 4, 0x6c, "Pkts256to511Octets" },
150 { 4, 0x70, "Pkts512to1023Octets" },
151 { 4, 0x74, "Pkts1024to1522Octets" },
152 { 4, 0x78, "RxOversizePkts" },
153 { 4, 0x7c, "RxJabbers" },
154 { 4, 0x80, "RxAlignmentErrors" },
155 { 4, 0x84, "RxFCSErrors" },
156 { 8, 0x88, "RxGoodOctets" },
157 { 4, 0x90, "RxDropPkts" },
158 { 4, 0x94, "RxUnicastPkts" },
159 { 4, 0x98, "RxMulticastPkts" },
160 { 4, 0x9c, "RxBroadcastPkts" },
161 { 4, 0xa0, "RxSAChanges" },
162 { 4, 0xa4, "RxFragments" },
163 { 4, 0xa8, "RxJumboPkts" },
164 { 4, 0xac, "RxSymbolErrors" },
165 { 4, 0xc0, "RxDiscarded" },
168 #define B53_MIBS_SIZE ARRAY_SIZE(b53_mibs)
170 static const struct b53_mib_desc b53_mibs_58xx[] = {
171 { 8, 0x00, "TxOctets" },
172 { 4, 0x08, "TxDropPkts" },
173 { 4, 0x0c, "TxQPKTQ0" },
174 { 4, 0x10, "TxBroadcastPkts" },
175 { 4, 0x14, "TxMulticastPkts" },
176 { 4, 0x18, "TxUnicastPKts" },
177 { 4, 0x1c, "TxCollisions" },
178 { 4, 0x20, "TxSingleCollision" },
179 { 4, 0x24, "TxMultipleCollision" },
180 { 4, 0x28, "TxDeferredCollision" },
181 { 4, 0x2c, "TxLateCollision" },
182 { 4, 0x30, "TxExcessiveCollision" },
183 { 4, 0x34, "TxFrameInDisc" },
184 { 4, 0x38, "TxPausePkts" },
185 { 4, 0x3c, "TxQPKTQ1" },
186 { 4, 0x40, "TxQPKTQ2" },
187 { 4, 0x44, "TxQPKTQ3" },
188 { 4, 0x48, "TxQPKTQ4" },
189 { 4, 0x4c, "TxQPKTQ5" },
190 { 8, 0x50, "RxOctets" },
191 { 4, 0x58, "RxUndersizePkts" },
192 { 4, 0x5c, "RxPausePkts" },
193 { 4, 0x60, "RxPkts64Octets" },
194 { 4, 0x64, "RxPkts65to127Octets" },
195 { 4, 0x68, "RxPkts128to255Octets" },
196 { 4, 0x6c, "RxPkts256to511Octets" },
197 { 4, 0x70, "RxPkts512to1023Octets" },
198 { 4, 0x74, "RxPkts1024toMaxPktsOctets" },
199 { 4, 0x78, "RxOversizePkts" },
200 { 4, 0x7c, "RxJabbers" },
201 { 4, 0x80, "RxAlignmentErrors" },
202 { 4, 0x84, "RxFCSErrors" },
203 { 8, 0x88, "RxGoodOctets" },
204 { 4, 0x90, "RxDropPkts" },
205 { 4, 0x94, "RxUnicastPkts" },
206 { 4, 0x98, "RxMulticastPkts" },
207 { 4, 0x9c, "RxBroadcastPkts" },
208 { 4, 0xa0, "RxSAChanges" },
209 { 4, 0xa4, "RxFragments" },
210 { 4, 0xa8, "RxJumboPkt" },
211 { 4, 0xac, "RxSymblErr" },
212 { 4, 0xb0, "InRangeErrCount" },
213 { 4, 0xb4, "OutRangeErrCount" },
214 { 4, 0xb8, "EEELpiEvent" },
215 { 4, 0xbc, "EEELpiDuration" },
216 { 4, 0xc0, "RxDiscard" },
217 { 4, 0xc8, "TxQPKTQ6" },
218 { 4, 0xcc, "TxQPKTQ7" },
219 { 4, 0xd0, "TxPkts64Octets" },
220 { 4, 0xd4, "TxPkts65to127Octets" },
221 { 4, 0xd8, "TxPkts128to255Octets" },
222 { 4, 0xdc, "TxPkts256to511Ocets" },
223 { 4, 0xe0, "TxPkts512to1023Ocets" },
224 { 4, 0xe4, "TxPkts1024toMaxPktOcets" },
227 #define B53_MIBS_58XX_SIZE ARRAY_SIZE(b53_mibs_58xx)
229 static int b53_do_vlan_op(struct b53_device *dev, u8 op)
233 b53_write8(dev, B53_ARLIO_PAGE, dev->vta_regs[0], VTA_START_CMD | op);
235 for (i = 0; i < 10; i++) {
238 b53_read8(dev, B53_ARLIO_PAGE, dev->vta_regs[0], &vta);
239 if (!(vta & VTA_START_CMD))
242 usleep_range(100, 200);
248 static void b53_set_vlan_entry(struct b53_device *dev, u16 vid,
249 struct b53_vlan *vlan)
255 entry = ((vlan->untag & VA_UNTAG_MASK_25) <<
256 VA_UNTAG_S_25) | vlan->members;
257 if (dev->core_rev >= 3)
258 entry |= VA_VALID_25_R4 | vid << VA_VID_HIGH_S;
260 entry |= VA_VALID_25;
263 b53_write32(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_25, entry);
264 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, vid |
265 VTA_RW_STATE_WR | VTA_RW_OP_EN);
266 } else if (is5365(dev)) {
270 entry = ((vlan->untag & VA_UNTAG_MASK_65) <<
271 VA_UNTAG_S_65) | vlan->members | VA_VALID_65;
273 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_65, entry);
274 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_65, vid |
275 VTA_RW_STATE_WR | VTA_RW_OP_EN);
277 b53_write16(dev, B53_ARLIO_PAGE, dev->vta_regs[1], vid);
278 b53_write32(dev, B53_ARLIO_PAGE, dev->vta_regs[2],
279 (vlan->untag << VTE_UNTAG_S) | vlan->members);
281 b53_do_vlan_op(dev, VTA_CMD_WRITE);
284 dev_dbg(dev->ds->dev, "VID: %d, members: 0x%04x, untag: 0x%04x\n",
285 vid, vlan->members, vlan->untag);
288 static void b53_get_vlan_entry(struct b53_device *dev, u16 vid,
289 struct b53_vlan *vlan)
294 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, vid |
295 VTA_RW_STATE_RD | VTA_RW_OP_EN);
296 b53_read32(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_25, &entry);
298 if (dev->core_rev >= 3)
299 vlan->valid = !!(entry & VA_VALID_25_R4);
301 vlan->valid = !!(entry & VA_VALID_25);
302 vlan->members = entry & VA_MEMBER_MASK;
303 vlan->untag = (entry >> VA_UNTAG_S_25) & VA_UNTAG_MASK_25;
305 } else if (is5365(dev)) {
308 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_65, vid |
309 VTA_RW_STATE_WR | VTA_RW_OP_EN);
310 b53_read16(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_65, &entry);
312 vlan->valid = !!(entry & VA_VALID_65);
313 vlan->members = entry & VA_MEMBER_MASK;
314 vlan->untag = (entry >> VA_UNTAG_S_65) & VA_UNTAG_MASK_65;
318 b53_write16(dev, B53_ARLIO_PAGE, dev->vta_regs[1], vid);
319 b53_do_vlan_op(dev, VTA_CMD_READ);
320 b53_read32(dev, B53_ARLIO_PAGE, dev->vta_regs[2], &entry);
321 vlan->members = entry & VTE_MEMBERS;
322 vlan->untag = (entry >> VTE_UNTAG_S) & VTE_MEMBERS;
327 static void b53_set_forwarding(struct b53_device *dev, int enable)
329 struct dsa_switch *ds = dev->ds;
332 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt);
335 mgmt |= SM_SW_FWD_EN;
337 mgmt &= ~SM_SW_FWD_EN;
339 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, mgmt);
341 /* Include IMP port in dumb forwarding mode when no tagging protocol is
344 if (ds->ops->get_tag_protocol(ds) == DSA_TAG_PROTO_NONE) {
345 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_CTRL, &mgmt);
346 mgmt |= B53_MII_DUMB_FWDG_EN;
347 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_CTRL, mgmt);
351 static void b53_enable_vlan(struct b53_device *dev, bool enable)
353 u8 mgmt, vc0, vc1, vc4 = 0, vc5;
355 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt);
356 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL0, &vc0);
357 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL1, &vc1);
359 if (is5325(dev) || is5365(dev)) {
360 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_25, &vc4);
361 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_25, &vc5);
362 } else if (is63xx(dev)) {
363 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_63XX, &vc4);
364 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_63XX, &vc5);
366 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4, &vc4);
367 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5, &vc5);
370 mgmt &= ~SM_SW_FWD_MODE;
373 vc0 |= VC0_VLAN_EN | VC0_VID_CHK_EN | VC0_VID_HASH_VID;
374 vc1 |= VC1_RX_MCST_UNTAG_EN | VC1_RX_MCST_FWD_EN;
375 vc4 &= ~VC4_ING_VID_CHECK_MASK;
376 vc4 |= VC4_ING_VID_VIO_DROP << VC4_ING_VID_CHECK_S;
377 vc5 |= VC5_DROP_VTABLE_MISS;
380 vc0 &= ~VC0_RESERVED_1;
382 if (is5325(dev) || is5365(dev))
383 vc1 |= VC1_RX_MCST_TAG_EN;
386 vc0 &= ~(VC0_VLAN_EN | VC0_VID_CHK_EN | VC0_VID_HASH_VID);
387 vc1 &= ~(VC1_RX_MCST_UNTAG_EN | VC1_RX_MCST_FWD_EN);
388 vc4 &= ~VC4_ING_VID_CHECK_MASK;
389 vc5 &= ~VC5_DROP_VTABLE_MISS;
391 if (is5325(dev) || is5365(dev))
392 vc4 |= VC4_ING_VID_VIO_FWD << VC4_ING_VID_CHECK_S;
394 vc4 |= VC4_ING_VID_VIO_TO_IMP << VC4_ING_VID_CHECK_S;
396 if (is5325(dev) || is5365(dev))
397 vc1 &= ~VC1_RX_MCST_TAG_EN;
400 if (!is5325(dev) && !is5365(dev))
401 vc5 &= ~VC5_VID_FFF_EN;
403 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL0, vc0);
404 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL1, vc1);
406 if (is5325(dev) || is5365(dev)) {
407 /* enable the high 8 bit vid check on 5325 */
408 if (is5325(dev) && enable)
409 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3,
412 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3, 0);
414 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_25, vc4);
415 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_25, vc5);
416 } else if (is63xx(dev)) {
417 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3_63XX, 0);
418 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_63XX, vc4);
419 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_63XX, vc5);
421 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3, 0);
422 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4, vc4);
423 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5, vc5);
426 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, mgmt);
429 static int b53_set_jumbo(struct b53_device *dev, bool enable, bool allow_10_100)
432 u16 max_size = JMS_MIN_SIZE;
434 if (is5325(dev) || is5365(dev))
438 port_mask = dev->enabled_ports;
439 max_size = JMS_MAX_SIZE;
441 port_mask |= JPM_10_100_JUMBO_EN;
444 b53_write32(dev, B53_JUMBO_PAGE, dev->jumbo_pm_reg, port_mask);
445 return b53_write16(dev, B53_JUMBO_PAGE, dev->jumbo_size_reg, max_size);
448 static int b53_flush_arl(struct b53_device *dev, u8 mask)
452 b53_write8(dev, B53_CTRL_PAGE, B53_FAST_AGE_CTRL,
453 FAST_AGE_DONE | FAST_AGE_DYNAMIC | mask);
455 for (i = 0; i < 10; i++) {
458 b53_read8(dev, B53_CTRL_PAGE, B53_FAST_AGE_CTRL,
461 if (!(fast_age_ctrl & FAST_AGE_DONE))
469 /* Only age dynamic entries (default behavior) */
470 b53_write8(dev, B53_CTRL_PAGE, B53_FAST_AGE_CTRL, FAST_AGE_DYNAMIC);
474 static int b53_fast_age_port(struct b53_device *dev, int port)
476 b53_write8(dev, B53_CTRL_PAGE, B53_FAST_AGE_PORT_CTRL, port);
478 return b53_flush_arl(dev, FAST_AGE_PORT);
481 static int b53_fast_age_vlan(struct b53_device *dev, u16 vid)
483 b53_write16(dev, B53_CTRL_PAGE, B53_FAST_AGE_VID_CTRL, vid);
485 return b53_flush_arl(dev, FAST_AGE_VLAN);
488 static void b53_imp_vlan_setup(struct dsa_switch *ds, int cpu_port)
490 struct b53_device *dev = ds->priv;
494 /* Enable the IMP port to be in the same VLAN as the other ports
495 * on a per-port basis such that we only have Port i and IMP in
498 b53_for_each_port(dev, i) {
499 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), &pvlan);
500 pvlan |= BIT(cpu_port);
501 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), pvlan);
505 static void b53_port_set_learning(struct b53_device *dev, int port,
510 b53_read16(dev, B53_CTRL_PAGE, B53_DIS_LEARNING, ®);
515 b53_write16(dev, B53_CTRL_PAGE, B53_DIS_LEARNING, reg);
518 static int b53_enable_port(struct dsa_switch *ds, int port,
519 struct phy_device *phy)
521 struct b53_device *dev = ds->priv;
522 unsigned int cpu_port = dev->cpu_port;
525 b53_port_set_learning(dev, port, false);
527 /* Clear the Rx and Tx disable bits and set to no spanning tree */
528 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), 0);
530 /* Set this port, and only this one to be in the default VLAN,
531 * if member of a bridge, restore its membership prior to
532 * bringing down this port.
534 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), &pvlan);
537 pvlan |= dev->ports[port].vlan_ctl_mask;
538 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), pvlan);
540 b53_imp_vlan_setup(ds, cpu_port);
545 static void b53_disable_port(struct dsa_switch *ds, int port,
546 struct phy_device *phy)
548 struct b53_device *dev = ds->priv;
551 /* Disable Tx/Rx for the port */
552 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), ®);
553 reg |= PORT_CTRL_RX_DISABLE | PORT_CTRL_TX_DISABLE;
554 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), reg);
557 static void b53_enable_cpu_port(struct b53_device *dev)
559 unsigned int cpu_port = dev->cpu_port;
562 /* BCM5325 CPU port is at 8 */
563 if ((is5325(dev) || is5365(dev)) && cpu_port == B53_CPU_PORT_25)
564 cpu_port = B53_CPU_PORT;
566 port_ctrl = PORT_CTRL_RX_BCST_EN |
567 PORT_CTRL_RX_MCST_EN |
568 PORT_CTRL_RX_UCST_EN;
569 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(cpu_port), port_ctrl);
571 b53_port_set_learning(dev, cpu_port, false);
574 static void b53_enable_mib(struct b53_device *dev)
578 b53_read8(dev, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, &gc);
579 gc &= ~(GC_RESET_MIB | GC_MIB_AC_EN);
580 b53_write8(dev, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, gc);
583 static int b53_configure_vlan(struct b53_device *dev)
585 struct b53_vlan vl = { 0 };
588 /* clear all vlan entries */
589 if (is5325(dev) || is5365(dev)) {
590 for (i = 1; i < dev->num_vlans; i++)
591 b53_set_vlan_entry(dev, i, &vl);
593 b53_do_vlan_op(dev, VTA_CMD_CLEAR);
596 b53_enable_vlan(dev, false);
598 b53_for_each_port(dev, i)
599 b53_write16(dev, B53_VLAN_PAGE,
600 B53_VLAN_PORT_DEF_TAG(i), 1);
602 if (!is5325(dev) && !is5365(dev))
603 b53_set_jumbo(dev, dev->enable_jumbo, false);
608 static void b53_switch_reset_gpio(struct b53_device *dev)
610 int gpio = dev->reset_gpio;
615 /* Reset sequence: RESET low(50ms)->high(20ms)
617 gpio_set_value(gpio, 0);
620 gpio_set_value(gpio, 1);
623 dev->current_page = 0xff;
626 static int b53_switch_reset(struct b53_device *dev)
630 b53_switch_reset_gpio(dev);
633 b53_write8(dev, B53_CTRL_PAGE, B53_SOFTRESET, 0x83);
634 b53_write8(dev, B53_CTRL_PAGE, B53_SOFTRESET, 0x00);
637 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt);
639 if (!(mgmt & SM_SW_FWD_EN)) {
640 mgmt &= ~SM_SW_FWD_MODE;
641 mgmt |= SM_SW_FWD_EN;
643 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, mgmt);
644 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt);
646 if (!(mgmt & SM_SW_FWD_EN)) {
647 dev_err(dev->dev, "Failed to enable switch!\n");
654 return b53_flush_arl(dev, FAST_AGE_STATIC);
657 static int b53_phy_read16(struct dsa_switch *ds, int addr, int reg)
659 struct b53_device *priv = ds->priv;
663 if (priv->ops->phy_read16)
664 ret = priv->ops->phy_read16(priv, addr, reg, &value);
666 ret = b53_read16(priv, B53_PORT_MII_PAGE(addr),
669 return ret ? ret : value;
672 static int b53_phy_write16(struct dsa_switch *ds, int addr, int reg, u16 val)
674 struct b53_device *priv = ds->priv;
676 if (priv->ops->phy_write16)
677 return priv->ops->phy_write16(priv, addr, reg, val);
679 return b53_write16(priv, B53_PORT_MII_PAGE(addr), reg * 2, val);
682 static int b53_reset_switch(struct b53_device *priv)
685 priv->enable_jumbo = false;
687 memset(priv->vlans, 0, sizeof(*priv->vlans) * priv->num_vlans);
688 memset(priv->ports, 0, sizeof(*priv->ports) * priv->num_ports);
690 return b53_switch_reset(priv);
693 static int b53_apply_config(struct b53_device *priv)
695 /* disable switching */
696 b53_set_forwarding(priv, 0);
698 b53_configure_vlan(priv);
700 /* enable switching */
701 b53_set_forwarding(priv, 1);
706 static void b53_reset_mib(struct b53_device *priv)
710 b53_read8(priv, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, &gc);
712 b53_write8(priv, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, gc | GC_RESET_MIB);
714 b53_write8(priv, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, gc & ~GC_RESET_MIB);
718 static const struct b53_mib_desc *b53_get_mib(struct b53_device *dev)
722 else if (is63xx(dev))
723 return b53_mibs_63xx;
724 else if (is58xx(dev))
725 return b53_mibs_58xx;
730 static unsigned int b53_get_mib_size(struct b53_device *dev)
733 return B53_MIBS_65_SIZE;
734 else if (is63xx(dev))
735 return B53_MIBS_63XX_SIZE;
736 else if (is58xx(dev))
737 return B53_MIBS_58XX_SIZE;
739 return B53_MIBS_SIZE;
742 static void b53_get_strings(struct dsa_switch *ds, int port, uint8_t *data)
744 struct b53_device *dev = ds->priv;
745 const struct b53_mib_desc *mibs = b53_get_mib(dev);
746 unsigned int mib_size = b53_get_mib_size(dev);
749 for (i = 0; i < mib_size; i++)
750 memcpy(data + i * ETH_GSTRING_LEN,
751 mibs[i].name, ETH_GSTRING_LEN);
754 static void b53_get_ethtool_stats(struct dsa_switch *ds, int port,
757 struct b53_device *dev = ds->priv;
758 const struct b53_mib_desc *mibs = b53_get_mib(dev);
759 unsigned int mib_size = b53_get_mib_size(dev);
760 const struct b53_mib_desc *s;
764 if (is5365(dev) && port == 5)
767 mutex_lock(&dev->stats_mutex);
769 for (i = 0; i < mib_size; i++) {
773 b53_read64(dev, B53_MIB_PAGE(port), s->offset, &val);
777 b53_read32(dev, B53_MIB_PAGE(port), s->offset,
784 mutex_unlock(&dev->stats_mutex);
787 static int b53_get_sset_count(struct dsa_switch *ds)
789 struct b53_device *dev = ds->priv;
791 return b53_get_mib_size(dev);
794 static int b53_setup(struct dsa_switch *ds)
796 struct b53_device *dev = ds->priv;
800 ret = b53_reset_switch(dev);
802 dev_err(ds->dev, "failed to reset switch\n");
808 ret = b53_apply_config(dev);
810 dev_err(ds->dev, "failed to apply configuration\n");
812 for (port = 0; port < dev->num_ports; port++) {
813 if (BIT(port) & ds->enabled_port_mask)
814 b53_enable_port(ds, port, NULL);
815 else if (dsa_is_cpu_port(ds, port))
816 b53_enable_cpu_port(dev);
818 b53_disable_port(ds, port, NULL);
824 static void b53_adjust_link(struct dsa_switch *ds, int port,
825 struct phy_device *phydev)
827 struct b53_device *dev = ds->priv;
828 u8 rgmii_ctrl = 0, reg = 0, off;
830 if (!phy_is_pseudo_fixed_link(phydev))
833 /* Override the port settings */
834 if (port == dev->cpu_port) {
835 off = B53_PORT_OVERRIDE_CTRL;
836 reg = PORT_OVERRIDE_EN;
838 off = B53_GMII_PORT_OVERRIDE_CTRL(port);
842 /* Set the link UP */
844 reg |= PORT_OVERRIDE_LINK;
846 if (phydev->duplex == DUPLEX_FULL)
847 reg |= PORT_OVERRIDE_FULL_DUPLEX;
849 switch (phydev->speed) {
851 reg |= PORT_OVERRIDE_SPEED_2000M;
854 reg |= PORT_OVERRIDE_SPEED_1000M;
857 reg |= PORT_OVERRIDE_SPEED_100M;
860 reg |= PORT_OVERRIDE_SPEED_10M;
863 dev_err(ds->dev, "unknown speed: %d\n", phydev->speed);
867 /* Enable flow control on BCM5301x's CPU port */
868 if (is5301x(dev) && port == dev->cpu_port)
869 reg |= PORT_OVERRIDE_RX_FLOW | PORT_OVERRIDE_TX_FLOW;
872 if (phydev->asym_pause)
873 reg |= PORT_OVERRIDE_TX_FLOW;
874 reg |= PORT_OVERRIDE_RX_FLOW;
877 b53_write8(dev, B53_CTRL_PAGE, off, reg);
879 if (is531x5(dev) && phy_interface_is_rgmii(phydev)) {
881 off = B53_RGMII_CTRL_IMP;
883 off = B53_RGMII_CTRL_P(port);
885 /* Configure the port RGMII clock delay by DLL disabled and
886 * tx_clk aligned timing (restoring to reset defaults)
888 b53_read8(dev, B53_CTRL_PAGE, off, &rgmii_ctrl);
889 rgmii_ctrl &= ~(RGMII_CTRL_DLL_RXC | RGMII_CTRL_DLL_TXC |
890 RGMII_CTRL_TIMING_SEL);
892 /* PHY_INTERFACE_MODE_RGMII_TXID means TX internal delay, make
893 * sure that we enable the port TX clock internal delay to
894 * account for this internal delay that is inserted, otherwise
895 * the switch won't be able to receive correctly.
897 * PHY_INTERFACE_MODE_RGMII means that we are not introducing
898 * any delay neither on transmission nor reception, so the
899 * BCM53125 must also be configured accordingly to account for
900 * the lack of delay and introduce
902 * The BCM53125 switch has its RX clock and TX clock control
903 * swapped, hence the reason why we modify the TX clock path in
906 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
907 rgmii_ctrl |= RGMII_CTRL_DLL_TXC;
908 if (phydev->interface == PHY_INTERFACE_MODE_RGMII)
909 rgmii_ctrl |= RGMII_CTRL_DLL_TXC | RGMII_CTRL_DLL_RXC;
910 rgmii_ctrl |= RGMII_CTRL_TIMING_SEL;
911 b53_write8(dev, B53_CTRL_PAGE, off, rgmii_ctrl);
913 dev_info(ds->dev, "Configured port %d for %s\n", port,
914 phy_modes(phydev->interface));
917 /* configure MII port if necessary */
919 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL,
922 /* reverse mii needs to be enabled */
923 if (!(reg & PORT_OVERRIDE_RV_MII_25)) {
924 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL,
925 reg | PORT_OVERRIDE_RV_MII_25);
926 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL,
929 if (!(reg & PORT_OVERRIDE_RV_MII_25)) {
931 "Failed to enable reverse MII mode\n");
935 } else if (is5301x(dev)) {
936 if (port != dev->cpu_port) {
937 u8 po_reg = B53_GMII_PORT_OVERRIDE_CTRL(dev->cpu_port);
940 b53_read8(dev, B53_CTRL_PAGE, po_reg, &gmii_po);
941 gmii_po |= GMII_PO_LINK |
946 b53_write8(dev, B53_CTRL_PAGE, po_reg, gmii_po);
951 static int b53_vlan_filtering(struct dsa_switch *ds, int port,
957 static int b53_vlan_prepare(struct dsa_switch *ds, int port,
958 const struct switchdev_obj_port_vlan *vlan,
959 struct switchdev_trans *trans)
961 struct b53_device *dev = ds->priv;
963 if ((is5325(dev) || is5365(dev)) && vlan->vid_begin == 0)
966 if (vlan->vid_end >= dev->num_vlans)
969 b53_enable_vlan(dev, true);
974 static void b53_vlan_add(struct dsa_switch *ds, int port,
975 const struct switchdev_obj_port_vlan *vlan,
976 struct switchdev_trans *trans)
978 struct b53_device *dev = ds->priv;
979 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
980 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID;
981 unsigned int cpu_port = dev->cpu_port;
985 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) {
986 vl = &dev->vlans[vid];
988 b53_get_vlan_entry(dev, vid, vl);
990 vl->members |= BIT(port) | BIT(cpu_port);
992 vl->untag |= BIT(port);
994 vl->untag &= ~BIT(port);
995 vl->untag &= ~BIT(cpu_port);
997 b53_set_vlan_entry(dev, vid, vl);
998 b53_fast_age_vlan(dev, vid);
1002 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_PORT_DEF_TAG(port),
1004 b53_fast_age_vlan(dev, vid);
1008 static int b53_vlan_del(struct dsa_switch *ds, int port,
1009 const struct switchdev_obj_port_vlan *vlan)
1011 struct b53_device *dev = ds->priv;
1012 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
1013 struct b53_vlan *vl;
1017 b53_read16(dev, B53_VLAN_PAGE, B53_VLAN_PORT_DEF_TAG(port), &pvid);
1019 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) {
1020 vl = &dev->vlans[vid];
1022 b53_get_vlan_entry(dev, vid, vl);
1024 vl->members &= ~BIT(port);
1027 if (is5325(dev) || is5365(dev))
1034 vl->untag &= ~(BIT(port));
1036 b53_set_vlan_entry(dev, vid, vl);
1037 b53_fast_age_vlan(dev, vid);
1040 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_PORT_DEF_TAG(port), pvid);
1041 b53_fast_age_vlan(dev, pvid);
1046 static int b53_vlan_dump(struct dsa_switch *ds, int port,
1047 struct switchdev_obj_port_vlan *vlan,
1048 int (*cb)(struct switchdev_obj *obj))
1050 struct b53_device *dev = ds->priv;
1051 u16 vid, vid_start = 0, pvid;
1052 struct b53_vlan *vl;
1055 if (is5325(dev) || is5365(dev))
1058 b53_read16(dev, B53_VLAN_PAGE, B53_VLAN_PORT_DEF_TAG(port), &pvid);
1060 /* Use our software cache for dumps, since we do not have any HW
1061 * operation returning only the used/valid VLANs
1063 for (vid = vid_start; vid < dev->num_vlans; vid++) {
1064 vl = &dev->vlans[vid];
1069 if (!(vl->members & BIT(port)))
1072 vlan->vid_begin = vlan->vid_end = vid;
1075 if (vl->untag & BIT(port))
1076 vlan->flags |= BRIDGE_VLAN_INFO_UNTAGGED;
1078 vlan->flags |= BRIDGE_VLAN_INFO_PVID;
1080 err = cb(&vlan->obj);
1088 /* Address Resolution Logic routines */
1089 static int b53_arl_op_wait(struct b53_device *dev)
1091 unsigned int timeout = 10;
1095 b53_read8(dev, B53_ARLIO_PAGE, B53_ARLTBL_RW_CTRL, ®);
1096 if (!(reg & ARLTBL_START_DONE))
1099 usleep_range(1000, 2000);
1100 } while (timeout--);
1102 dev_warn(dev->dev, "timeout waiting for ARL to finish: 0x%02x\n", reg);
1107 static int b53_arl_rw_op(struct b53_device *dev, unsigned int op)
1114 b53_read8(dev, B53_ARLIO_PAGE, B53_ARLTBL_RW_CTRL, ®);
1115 reg |= ARLTBL_START_DONE;
1120 b53_write8(dev, B53_ARLIO_PAGE, B53_ARLTBL_RW_CTRL, reg);
1122 return b53_arl_op_wait(dev);
1125 static int b53_arl_read(struct b53_device *dev, u64 mac,
1126 u16 vid, struct b53_arl_entry *ent, u8 *idx,
1129 DECLARE_BITMAP(free_bins, B53_ARLTBL_MAX_BIN_ENTRIES);
1133 ret = b53_arl_op_wait(dev);
1137 bitmap_zero(free_bins, dev->num_arl_entries);
1140 for (i = 0; i < dev->num_arl_entries; i++) {
1144 b53_read64(dev, B53_ARLIO_PAGE,
1145 B53_ARLTBL_MAC_VID_ENTRY(i), &mac_vid);
1146 b53_read32(dev, B53_ARLIO_PAGE,
1147 B53_ARLTBL_DATA_ENTRY(i), &fwd_entry);
1148 b53_arl_to_entry(ent, mac_vid, fwd_entry);
1150 if (!(fwd_entry & ARLTBL_VALID)) {
1151 set_bit(i, free_bins);
1154 if ((mac_vid & ARLTBL_MAC_MASK) != mac)
1160 if (bitmap_weight(free_bins, dev->num_arl_entries) == 0)
1163 *idx = find_first_bit(free_bins, dev->num_arl_entries);
1168 static int b53_arl_op(struct b53_device *dev, int op, int port,
1169 const unsigned char *addr, u16 vid, bool is_valid)
1171 struct b53_arl_entry ent;
1173 u64 mac, mac_vid = 0;
1177 /* Convert the array into a 64-bit MAC */
1178 mac = b53_mac_to_u64(addr);
1180 /* Perform a read for the given MAC and VID */
1181 b53_write48(dev, B53_ARLIO_PAGE, B53_MAC_ADDR_IDX, mac);
1182 b53_write16(dev, B53_ARLIO_PAGE, B53_VLAN_ID_IDX, vid);
1184 /* Issue a read operation for this MAC */
1185 ret = b53_arl_rw_op(dev, 1);
1189 ret = b53_arl_read(dev, mac, vid, &ent, &idx, is_valid);
1190 /* If this is a read, just finish now */
1198 dev_dbg(dev->dev, "{%pM,%.4d} no space left in ARL\n",
1200 return is_valid ? ret : 0;
1202 /* We could not find a matching MAC, so reset to a new entry */
1203 dev_dbg(dev->dev, "{%pM,%.4d} not found, using idx: %d\n",
1208 dev_dbg(dev->dev, "{%pM,%.4d} found, using idx: %d\n",
1213 memset(&ent, 0, sizeof(ent));
1215 ent.is_valid = is_valid;
1217 ent.is_static = true;
1218 memcpy(ent.mac, addr, ETH_ALEN);
1219 b53_arl_from_entry(&mac_vid, &fwd_entry, &ent);
1221 b53_write64(dev, B53_ARLIO_PAGE,
1222 B53_ARLTBL_MAC_VID_ENTRY(idx), mac_vid);
1223 b53_write32(dev, B53_ARLIO_PAGE,
1224 B53_ARLTBL_DATA_ENTRY(idx), fwd_entry);
1226 return b53_arl_rw_op(dev, 0);
1229 static int b53_fdb_prepare(struct dsa_switch *ds, int port,
1230 const struct switchdev_obj_port_fdb *fdb,
1231 struct switchdev_trans *trans)
1233 struct b53_device *priv = ds->priv;
1235 /* 5325 and 5365 require some more massaging, but could
1236 * be supported eventually
1238 if (is5325(priv) || is5365(priv))
1244 static void b53_fdb_add(struct dsa_switch *ds, int port,
1245 const struct switchdev_obj_port_fdb *fdb,
1246 struct switchdev_trans *trans)
1248 struct b53_device *priv = ds->priv;
1250 if (b53_arl_op(priv, 0, port, fdb->addr, fdb->vid, true))
1251 pr_err("%s: failed to add MAC address\n", __func__);
1254 static int b53_fdb_del(struct dsa_switch *ds, int port,
1255 const struct switchdev_obj_port_fdb *fdb)
1257 struct b53_device *priv = ds->priv;
1259 return b53_arl_op(priv, 0, port, fdb->addr, fdb->vid, false);
1262 static int b53_arl_search_wait(struct b53_device *dev)
1264 unsigned int timeout = 1000;
1268 b53_read8(dev, B53_ARLIO_PAGE, B53_ARL_SRCH_CTL, ®);
1269 if (!(reg & ARL_SRCH_STDN))
1272 if (reg & ARL_SRCH_VLID)
1275 usleep_range(1000, 2000);
1276 } while (timeout--);
1281 static void b53_arl_search_rd(struct b53_device *dev, u8 idx,
1282 struct b53_arl_entry *ent)
1287 b53_read64(dev, B53_ARLIO_PAGE,
1288 B53_ARL_SRCH_RSTL_MACVID(idx), &mac_vid);
1289 b53_read32(dev, B53_ARLIO_PAGE,
1290 B53_ARL_SRCH_RSTL(idx), &fwd_entry);
1291 b53_arl_to_entry(ent, mac_vid, fwd_entry);
1294 static int b53_fdb_copy(struct net_device *dev, int port,
1295 const struct b53_arl_entry *ent,
1296 struct switchdev_obj_port_fdb *fdb,
1297 int (*cb)(struct switchdev_obj *obj))
1302 if (port != ent->port)
1305 ether_addr_copy(fdb->addr, ent->mac);
1306 fdb->vid = ent->vid;
1307 fdb->ndm_state = ent->is_static ? NUD_NOARP : NUD_REACHABLE;
1309 return cb(&fdb->obj);
1312 static int b53_fdb_dump(struct dsa_switch *ds, int port,
1313 struct switchdev_obj_port_fdb *fdb,
1314 int (*cb)(struct switchdev_obj *obj))
1316 struct b53_device *priv = ds->priv;
1317 struct net_device *dev = ds->ports[port].netdev;
1318 struct b53_arl_entry results[2];
1319 unsigned int count = 0;
1323 /* Start search operation */
1324 reg = ARL_SRCH_STDN;
1325 b53_write8(priv, B53_ARLIO_PAGE, B53_ARL_SRCH_CTL, reg);
1328 ret = b53_arl_search_wait(priv);
1332 b53_arl_search_rd(priv, 0, &results[0]);
1333 ret = b53_fdb_copy(dev, port, &results[0], fdb, cb);
1337 if (priv->num_arl_entries > 2) {
1338 b53_arl_search_rd(priv, 1, &results[1]);
1339 ret = b53_fdb_copy(dev, port, &results[1], fdb, cb);
1343 if (!results[0].is_valid && !results[1].is_valid)
1347 } while (count++ < 1024);
1352 static int b53_br_join(struct dsa_switch *ds, int port,
1353 struct net_device *bridge)
1355 struct b53_device *dev = ds->priv;
1356 s8 cpu_port = ds->dst->cpu_port;
1360 /* Make this port leave the all VLANs join since we will have proper
1361 * VLAN entries from now on
1364 b53_read16(dev, B53_VLAN_PAGE, B53_JOIN_ALL_VLAN_EN, ®);
1366 if ((reg & BIT(cpu_port)) == BIT(cpu_port))
1367 reg &= ~BIT(cpu_port);
1368 b53_write16(dev, B53_VLAN_PAGE, B53_JOIN_ALL_VLAN_EN, reg);
1371 dev->ports[port].bridge_dev = bridge;
1372 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), &pvlan);
1374 b53_for_each_port(dev, i) {
1375 if (dev->ports[i].bridge_dev != bridge)
1378 /* Add this local port to the remote port VLAN control
1379 * membership and update the remote port bitmask
1381 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), ®);
1383 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), reg);
1384 dev->ports[i].vlan_ctl_mask = reg;
1389 /* Configure the local port VLAN control membership to include
1390 * remote ports and update the local port bitmask
1392 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), pvlan);
1393 dev->ports[port].vlan_ctl_mask = pvlan;
1395 b53_port_set_learning(dev, port, true);
1400 static void b53_br_leave(struct dsa_switch *ds, int port)
1402 struct b53_device *dev = ds->priv;
1403 struct net_device *bridge = dev->ports[port].bridge_dev;
1404 struct b53_vlan *vl = &dev->vlans[0];
1405 s8 cpu_port = ds->dst->cpu_port;
1407 u16 pvlan, reg, pvid;
1409 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), &pvlan);
1411 b53_for_each_port(dev, i) {
1412 /* Don't touch the remaining ports */
1413 if (dev->ports[i].bridge_dev != bridge)
1416 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), ®);
1418 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), reg);
1419 dev->ports[port].vlan_ctl_mask = reg;
1421 /* Prevent self removal to preserve isolation */
1426 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), pvlan);
1427 dev->ports[port].vlan_ctl_mask = pvlan;
1428 dev->ports[port].bridge_dev = NULL;
1430 if (is5325(dev) || is5365(dev))
1435 /* Make this port join all VLANs without VLAN entries */
1437 b53_read16(dev, B53_VLAN_PAGE, B53_JOIN_ALL_VLAN_EN, ®);
1439 if (!(reg & BIT(cpu_port)))
1440 reg |= BIT(cpu_port);
1441 b53_write16(dev, B53_VLAN_PAGE, B53_JOIN_ALL_VLAN_EN, reg);
1443 b53_get_vlan_entry(dev, pvid, vl);
1444 vl->members |= BIT(port) | BIT(dev->cpu_port);
1445 vl->untag |= BIT(port) | BIT(dev->cpu_port);
1446 b53_set_vlan_entry(dev, pvid, vl);
1448 b53_port_set_learning(dev, port, false);
1451 static void b53_br_set_stp_state(struct dsa_switch *ds, int port, u8 state)
1453 struct b53_device *dev = ds->priv;
1458 case BR_STATE_DISABLED:
1459 hw_state = PORT_CTRL_DIS_STATE;
1461 case BR_STATE_LISTENING:
1462 hw_state = PORT_CTRL_LISTEN_STATE;
1464 case BR_STATE_LEARNING:
1465 hw_state = PORT_CTRL_LEARN_STATE;
1467 case BR_STATE_FORWARDING:
1468 hw_state = PORT_CTRL_FWD_STATE;
1470 case BR_STATE_BLOCKING:
1471 hw_state = PORT_CTRL_BLOCK_STATE;
1474 dev_err(ds->dev, "invalid STP state: %d\n", state);
1478 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), ®);
1479 reg &= ~PORT_CTRL_STP_STATE_MASK;
1481 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), reg);
1484 static void b53_br_fast_age(struct dsa_switch *ds, int port)
1486 struct b53_device *dev = ds->priv;
1488 if (b53_fast_age_port(dev, port))
1489 dev_err(ds->dev, "fast ageing failed\n");
1492 static enum dsa_tag_protocol b53_get_tag_protocol(struct dsa_switch *ds)
1494 return DSA_TAG_PROTO_NONE;
1497 static struct dsa_switch_ops b53_switch_ops = {
1498 .get_tag_protocol = b53_get_tag_protocol,
1500 .get_strings = b53_get_strings,
1501 .get_ethtool_stats = b53_get_ethtool_stats,
1502 .get_sset_count = b53_get_sset_count,
1503 .phy_read = b53_phy_read16,
1504 .phy_write = b53_phy_write16,
1505 .adjust_link = b53_adjust_link,
1506 .port_enable = b53_enable_port,
1507 .port_disable = b53_disable_port,
1508 .port_bridge_join = b53_br_join,
1509 .port_bridge_leave = b53_br_leave,
1510 .port_stp_state_set = b53_br_set_stp_state,
1511 .port_fast_age = b53_br_fast_age,
1512 .port_vlan_filtering = b53_vlan_filtering,
1513 .port_vlan_prepare = b53_vlan_prepare,
1514 .port_vlan_add = b53_vlan_add,
1515 .port_vlan_del = b53_vlan_del,
1516 .port_vlan_dump = b53_vlan_dump,
1517 .port_fdb_prepare = b53_fdb_prepare,
1518 .port_fdb_dump = b53_fdb_dump,
1519 .port_fdb_add = b53_fdb_add,
1520 .port_fdb_del = b53_fdb_del,
1523 struct b53_chip_data {
1525 const char *dev_name;
1536 #define B53_VTA_REGS \
1537 { B53_VT_ACCESS, B53_VT_INDEX, B53_VT_ENTRY }
1538 #define B53_VTA_REGS_9798 \
1539 { B53_VT_ACCESS_9798, B53_VT_INDEX_9798, B53_VT_ENTRY_9798 }
1540 #define B53_VTA_REGS_63XX \
1541 { B53_VT_ACCESS_63XX, B53_VT_INDEX_63XX, B53_VT_ENTRY_63XX }
1543 static const struct b53_chip_data b53_switch_chips[] = {
1545 .chip_id = BCM5325_DEVICE_ID,
1546 .dev_name = "BCM5325",
1548 .enabled_ports = 0x1f,
1550 .cpu_port = B53_CPU_PORT_25,
1551 .duplex_reg = B53_DUPLEX_STAT_FE,
1554 .chip_id = BCM5365_DEVICE_ID,
1555 .dev_name = "BCM5365",
1557 .enabled_ports = 0x1f,
1559 .cpu_port = B53_CPU_PORT_25,
1560 .duplex_reg = B53_DUPLEX_STAT_FE,
1563 .chip_id = BCM5389_DEVICE_ID,
1564 .dev_name = "BCM5389",
1566 .enabled_ports = 0x1f,
1568 .cpu_port = B53_CPU_PORT,
1569 .vta_regs = B53_VTA_REGS,
1570 .duplex_reg = B53_DUPLEX_STAT_GE,
1571 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1572 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1575 .chip_id = BCM5395_DEVICE_ID,
1576 .dev_name = "BCM5395",
1578 .enabled_ports = 0x1f,
1580 .cpu_port = B53_CPU_PORT,
1581 .vta_regs = B53_VTA_REGS,
1582 .duplex_reg = B53_DUPLEX_STAT_GE,
1583 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1584 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1587 .chip_id = BCM5397_DEVICE_ID,
1588 .dev_name = "BCM5397",
1590 .enabled_ports = 0x1f,
1592 .cpu_port = B53_CPU_PORT,
1593 .vta_regs = B53_VTA_REGS_9798,
1594 .duplex_reg = B53_DUPLEX_STAT_GE,
1595 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1596 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1599 .chip_id = BCM5398_DEVICE_ID,
1600 .dev_name = "BCM5398",
1602 .enabled_ports = 0x7f,
1604 .cpu_port = B53_CPU_PORT,
1605 .vta_regs = B53_VTA_REGS_9798,
1606 .duplex_reg = B53_DUPLEX_STAT_GE,
1607 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1608 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1611 .chip_id = BCM53115_DEVICE_ID,
1612 .dev_name = "BCM53115",
1614 .enabled_ports = 0x1f,
1616 .vta_regs = B53_VTA_REGS,
1617 .cpu_port = B53_CPU_PORT,
1618 .duplex_reg = B53_DUPLEX_STAT_GE,
1619 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1620 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1623 .chip_id = BCM53125_DEVICE_ID,
1624 .dev_name = "BCM53125",
1626 .enabled_ports = 0xff,
1628 .cpu_port = B53_CPU_PORT,
1629 .vta_regs = B53_VTA_REGS,
1630 .duplex_reg = B53_DUPLEX_STAT_GE,
1631 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1632 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1635 .chip_id = BCM53128_DEVICE_ID,
1636 .dev_name = "BCM53128",
1638 .enabled_ports = 0x1ff,
1640 .cpu_port = B53_CPU_PORT,
1641 .vta_regs = B53_VTA_REGS,
1642 .duplex_reg = B53_DUPLEX_STAT_GE,
1643 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1644 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1647 .chip_id = BCM63XX_DEVICE_ID,
1648 .dev_name = "BCM63xx",
1650 .enabled_ports = 0, /* pdata must provide them */
1652 .cpu_port = B53_CPU_PORT,
1653 .vta_regs = B53_VTA_REGS_63XX,
1654 .duplex_reg = B53_DUPLEX_STAT_63XX,
1655 .jumbo_pm_reg = B53_JUMBO_PORT_MASK_63XX,
1656 .jumbo_size_reg = B53_JUMBO_MAX_SIZE_63XX,
1659 .chip_id = BCM53010_DEVICE_ID,
1660 .dev_name = "BCM53010",
1662 .enabled_ports = 0x1f,
1664 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */
1665 .vta_regs = B53_VTA_REGS,
1666 .duplex_reg = B53_DUPLEX_STAT_GE,
1667 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1668 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1671 .chip_id = BCM53011_DEVICE_ID,
1672 .dev_name = "BCM53011",
1674 .enabled_ports = 0x1bf,
1676 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */
1677 .vta_regs = B53_VTA_REGS,
1678 .duplex_reg = B53_DUPLEX_STAT_GE,
1679 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1680 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1683 .chip_id = BCM53012_DEVICE_ID,
1684 .dev_name = "BCM53012",
1686 .enabled_ports = 0x1bf,
1688 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */
1689 .vta_regs = B53_VTA_REGS,
1690 .duplex_reg = B53_DUPLEX_STAT_GE,
1691 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1692 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1695 .chip_id = BCM53018_DEVICE_ID,
1696 .dev_name = "BCM53018",
1698 .enabled_ports = 0x1f,
1700 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */
1701 .vta_regs = B53_VTA_REGS,
1702 .duplex_reg = B53_DUPLEX_STAT_GE,
1703 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1704 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1707 .chip_id = BCM53019_DEVICE_ID,
1708 .dev_name = "BCM53019",
1710 .enabled_ports = 0x1f,
1712 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */
1713 .vta_regs = B53_VTA_REGS,
1714 .duplex_reg = B53_DUPLEX_STAT_GE,
1715 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1716 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1719 .chip_id = BCM58XX_DEVICE_ID,
1720 .dev_name = "BCM585xx/586xx/88312",
1722 .enabled_ports = 0x1ff,
1724 .cpu_port = B53_CPU_PORT_25,
1725 .vta_regs = B53_VTA_REGS,
1726 .duplex_reg = B53_DUPLEX_STAT_GE,
1727 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1728 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1731 .chip_id = BCM7445_DEVICE_ID,
1732 .dev_name = "BCM7445",
1734 .enabled_ports = 0x1ff,
1736 .cpu_port = B53_CPU_PORT,
1737 .vta_regs = B53_VTA_REGS,
1738 .duplex_reg = B53_DUPLEX_STAT_GE,
1739 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1740 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1744 static int b53_switch_init(struct b53_device *dev)
1749 for (i = 0; i < ARRAY_SIZE(b53_switch_chips); i++) {
1750 const struct b53_chip_data *chip = &b53_switch_chips[i];
1752 if (chip->chip_id == dev->chip_id) {
1753 if (!dev->enabled_ports)
1754 dev->enabled_ports = chip->enabled_ports;
1755 dev->name = chip->dev_name;
1756 dev->duplex_reg = chip->duplex_reg;
1757 dev->vta_regs[0] = chip->vta_regs[0];
1758 dev->vta_regs[1] = chip->vta_regs[1];
1759 dev->vta_regs[2] = chip->vta_regs[2];
1760 dev->jumbo_pm_reg = chip->jumbo_pm_reg;
1761 dev->cpu_port = chip->cpu_port;
1762 dev->num_vlans = chip->vlans;
1763 dev->num_arl_entries = chip->arl_entries;
1768 /* check which BCM5325x version we have */
1772 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_25, &vc4);
1774 /* check reserved bits */
1780 /* BCM5325F - do not use port 4 */
1781 dev->enabled_ports &= ~BIT(4);
1784 /* On the BCM47XX SoCs this is the supported internal switch.*/
1785 #ifndef CONFIG_BCM47XX
1792 } else if (dev->chip_id == BCM53115_DEVICE_ID) {
1795 b53_read48(dev, B53_STAT_PAGE, B53_STRAP_VALUE, &strap_value);
1796 /* use second IMP port if GMII is enabled */
1797 if (strap_value & SV_GMII_CTRL_115)
1801 dev->enabled_ports |= BIT(dev->cpu_port);
1802 dev->num_ports = fls(dev->enabled_ports);
1804 dev->ports = devm_kzalloc(dev->dev,
1805 sizeof(struct b53_port) * dev->num_ports,
1810 dev->vlans = devm_kzalloc(dev->dev,
1811 sizeof(struct b53_vlan) * dev->num_vlans,
1816 dev->reset_gpio = b53_switch_get_reset_gpio(dev);
1817 if (dev->reset_gpio >= 0) {
1818 ret = devm_gpio_request_one(dev->dev, dev->reset_gpio,
1819 GPIOF_OUT_INIT_HIGH, "robo_reset");
1827 struct b53_device *b53_switch_alloc(struct device *base,
1828 const struct b53_io_ops *ops,
1831 struct dsa_switch *ds;
1832 struct b53_device *dev;
1834 ds = devm_kzalloc(base, sizeof(*ds) + sizeof(*dev), GFP_KERNEL);
1838 dev = (struct b53_device *)(ds + 1);
1847 ds->ops = &b53_switch_ops;
1848 mutex_init(&dev->reg_mutex);
1849 mutex_init(&dev->stats_mutex);
1853 EXPORT_SYMBOL(b53_switch_alloc);
1855 int b53_switch_detect(struct b53_device *dev)
1862 ret = b53_read8(dev, B53_MGMT_PAGE, B53_DEVICE_ID, &id8);
1868 /* BCM5325 and BCM5365 do not have this register so reads
1869 * return 0. But the read operation did succeed, so assume this
1872 * Next check if we can write to the 5325's VTA register; for
1873 * 5365 it is read only.
1875 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, 0xf);
1876 b53_read16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, &tmp);
1879 dev->chip_id = BCM5325_DEVICE_ID;
1881 dev->chip_id = BCM5365_DEVICE_ID;
1883 case BCM5389_DEVICE_ID:
1884 case BCM5395_DEVICE_ID:
1885 case BCM5397_DEVICE_ID:
1886 case BCM5398_DEVICE_ID:
1890 ret = b53_read32(dev, B53_MGMT_PAGE, B53_DEVICE_ID, &id32);
1895 case BCM53115_DEVICE_ID:
1896 case BCM53125_DEVICE_ID:
1897 case BCM53128_DEVICE_ID:
1898 case BCM53010_DEVICE_ID:
1899 case BCM53011_DEVICE_ID:
1900 case BCM53012_DEVICE_ID:
1901 case BCM53018_DEVICE_ID:
1902 case BCM53019_DEVICE_ID:
1903 dev->chip_id = id32;
1906 pr_err("unsupported switch detected (BCM53%02x/BCM%x)\n",
1912 if (dev->chip_id == BCM5325_DEVICE_ID)
1913 return b53_read8(dev, B53_STAT_PAGE, B53_REV_ID_25,
1916 return b53_read8(dev, B53_MGMT_PAGE, B53_REV_ID,
1919 EXPORT_SYMBOL(b53_switch_detect);
1921 int b53_switch_register(struct b53_device *dev)
1926 dev->chip_id = dev->pdata->chip_id;
1927 dev->enabled_ports = dev->pdata->enabled_ports;
1930 if (!dev->chip_id && b53_switch_detect(dev))
1933 ret = b53_switch_init(dev);
1937 pr_info("found switch: %s, rev %i\n", dev->name, dev->core_rev);
1939 return dsa_register_switch(dev->ds, dev->ds->dev->of_node);
1941 EXPORT_SYMBOL(b53_switch_register);
1943 MODULE_AUTHOR("Jonas Gorski <jogo@openwrt.org>");
1944 MODULE_DESCRIPTION("B53 switch library");
1945 MODULE_LICENSE("Dual BSD/GPL");