2 * Driver for Atmel I2S controller
4 * Copyright (C) 2015 Atmel Corporation
6 * Author: Cyrille Pitchen <cyrille.pitchen@atmel.com>
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License version 2 as published by
10 * the Free Software Foundation.
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
17 * You should have received a copy of the GNU General Public License along with
18 * this program. If not, see <http://www.gnu.org/licenses/>.
21 #include <linux/init.h>
22 #include <linux/module.h>
23 #include <linux/device.h>
24 #include <linux/slab.h>
25 #include <linux/delay.h>
27 #include <linux/clk.h>
28 #include <linux/mfd/syscon.h>
30 #include <sound/core.h>
31 #include <sound/pcm.h>
32 #include <sound/pcm_params.h>
33 #include <sound/initval.h>
34 #include <sound/soc.h>
35 #include <sound/dmaengine_pcm.h>
37 #define ATMEL_I2SC_MAX_TDM_CHANNELS 8
40 * ---- I2S Controller Register map ----
42 #define ATMEL_I2SC_CR 0x0000 /* Control Register */
43 #define ATMEL_I2SC_MR 0x0004 /* Mode Register */
44 #define ATMEL_I2SC_SR 0x0008 /* Status Register */
45 #define ATMEL_I2SC_SCR 0x000c /* Status Clear Register */
46 #define ATMEL_I2SC_SSR 0x0010 /* Status Set Register */
47 #define ATMEL_I2SC_IER 0x0014 /* Interrupt Enable Register */
48 #define ATMEL_I2SC_IDR 0x0018 /* Interrupt Disable Register */
49 #define ATMEL_I2SC_IMR 0x001c /* Interrupt Mask Register */
50 #define ATMEL_I2SC_RHR 0x0020 /* Receiver Holding Register */
51 #define ATMEL_I2SC_THR 0x0024 /* Transmitter Holding Register */
52 #define ATMEL_I2SC_VERSION 0x0028 /* Version Register */
55 * ---- Control Register (Write-only) ----
57 #define ATMEL_I2SC_CR_RXEN BIT(0) /* Receiver Enable */
58 #define ATMEL_I2SC_CR_RXDIS BIT(1) /* Receiver Disable */
59 #define ATMEL_I2SC_CR_CKEN BIT(2) /* Clock Enable */
60 #define ATMEL_I2SC_CR_CKDIS BIT(3) /* Clock Disable */
61 #define ATMEL_I2SC_CR_TXEN BIT(4) /* Transmitter Enable */
62 #define ATMEL_I2SC_CR_TXDIS BIT(5) /* Transmitter Disable */
63 #define ATMEL_I2SC_CR_SWRST BIT(7) /* Software Reset */
66 * ---- Mode Register (Read/Write) ----
68 #define ATMEL_I2SC_MR_MODE_MASK GENMASK(0, 0)
69 #define ATMEL_I2SC_MR_MODE_SLAVE (0 << 0)
70 #define ATMEL_I2SC_MR_MODE_MASTER (1 << 0)
72 #define ATMEL_I2SC_MR_DATALENGTH_MASK GENMASK(4, 2)
73 #define ATMEL_I2SC_MR_DATALENGTH_32_BITS (0 << 2)
74 #define ATMEL_I2SC_MR_DATALENGTH_24_BITS (1 << 2)
75 #define ATMEL_I2SC_MR_DATALENGTH_20_BITS (2 << 2)
76 #define ATMEL_I2SC_MR_DATALENGTH_18_BITS (3 << 2)
77 #define ATMEL_I2SC_MR_DATALENGTH_16_BITS (4 << 2)
78 #define ATMEL_I2SC_MR_DATALENGTH_16_BITS_COMPACT (5 << 2)
79 #define ATMEL_I2SC_MR_DATALENGTH_8_BITS (6 << 2)
80 #define ATMEL_I2SC_MR_DATALENGTH_8_BITS_COMPACT (7 << 2)
82 #define ATMEL_I2SC_MR_FORMAT_MASK GENMASK(7, 6)
83 #define ATMEL_I2SC_MR_FORMAT_I2S (0 << 6)
84 #define ATMEL_I2SC_MR_FORMAT_LJ (1 << 6) /* Left Justified */
85 #define ATMEL_I2SC_MR_FORMAT_TDM (2 << 6)
86 #define ATMEL_I2SC_MR_FORMAT_TDMLJ (3 << 6)
88 /* Left audio samples duplicated to right audio channel */
89 #define ATMEL_I2SC_MR_RXMONO BIT(8)
91 /* Receiver uses one DMA channel ... */
92 #define ATMEL_I2SC_MR_RXDMA_MASK GENMASK(9, 9)
93 #define ATMEL_I2SC_MR_RXDMA_SINGLE (0 << 9) /* for all audio channels */
94 #define ATMEL_I2SC_MR_RXDMA_MULTIPLE (1 << 9) /* per audio channel */
96 /* I2SDO output of I2SC is internally connected to I2SDI input */
97 #define ATMEL_I2SC_MR_RXLOOP BIT(10)
99 /* Left audio samples duplicated to right audio channel */
100 #define ATMEL_I2SC_MR_TXMONO BIT(12)
102 /* Transmitter uses one DMA channel ... */
103 #define ATMEL_I2SC_MR_TXDMA_MASK GENMASK(13, 13)
104 #define ATMEL_I2SC_MR_TXDMA_SINGLE (0 << 13) /* for all audio channels */
105 #define ATMEL_I2SC_MR_TXDME_MULTIPLE (1 << 13) /* per audio channel */
107 /* x sample transmitted when underrun */
108 #define ATMEL_I2SC_MR_TXSAME_MASK GENMASK(14, 14)
109 #define ATMEL_I2SC_MR_TXSAME_ZERO (0 << 14) /* Zero sample */
110 #define ATMEL_I2SC_MR_TXSAME_PREVIOUS (1 << 14) /* Previous sample */
112 /* Audio Clock to I2SC Master Clock ratio */
113 #define ATMEL_I2SC_MR_IMCKDIV_MASK GENMASK(21, 16)
114 #define ATMEL_I2SC_MR_IMCKDIV(div) \
115 (((div) << 16) & ATMEL_I2SC_MR_IMCKDIV_MASK)
117 /* Master Clock to fs ratio */
118 #define ATMEL_I2SC_MR_IMCKFS_MASK GENMASK(29, 24)
119 #define ATMEL_I2SC_MR_IMCKFS(fs) \
120 (((fs) << 24) & ATMEL_I2SC_MR_IMCKFS_MASK)
122 /* Master Clock mode */
123 #define ATMEL_I2SC_MR_IMCKMODE_MASK GENMASK(30, 30)
124 /* 0: No master clock generated (selected clock drives I2SCK pin) */
125 #define ATMEL_I2SC_MR_IMCKMODE_I2SCK (0 << 30)
126 /* 1: master clock generated (internally generated clock drives I2SMCK pin) */
127 #define ATMEL_I2SC_MR_IMCKMODE_I2SMCK (1 << 30)
130 /* 0: slot is 32 bits wide for DATALENGTH = 18/20/24 bits. */
131 /* 1: slot is 24 bits wide for DATALENGTH = 18/20/24 bits. */
132 #define ATMEL_I2SC_MR_IWS BIT(31)
135 * ---- Status Registers ----
137 #define ATMEL_I2SC_SR_RXEN BIT(0) /* Receiver Enabled */
138 #define ATMEL_I2SC_SR_RXRDY BIT(1) /* Receive Ready */
139 #define ATMEL_I2SC_SR_RXOR BIT(2) /* Receive Overrun */
141 #define ATMEL_I2SC_SR_TXEN BIT(4) /* Transmitter Enabled */
142 #define ATMEL_I2SC_SR_TXRDY BIT(5) /* Transmit Ready */
143 #define ATMEL_I2SC_SR_TXUR BIT(6) /* Transmit Underrun */
145 /* Receive Overrun Channel */
146 #define ATMEL_I2SC_SR_RXORCH_MASK GENMASK(15, 8)
147 #define ATMEL_I2SC_SR_RXORCH(ch) (1 << (((ch) & 0x7) + 8))
149 /* Transmit Underrun Channel */
150 #define ATMEL_I2SC_SR_TXURCH_MASK GENMASK(27, 20)
151 #define ATMEL_I2SC_SR_TXURCH(ch) (1 << (((ch) & 0x7) + 20))
154 * ---- Interrupt Enable/Disable/Mask Registers ----
156 #define ATMEL_I2SC_INT_RXRDY ATMEL_I2SC_SR_RXRDY
157 #define ATMEL_I2SC_INT_RXOR ATMEL_I2SC_SR_RXOR
158 #define ATMEL_I2SC_INT_TXRDY ATMEL_I2SC_SR_TXRDY
159 #define ATMEL_I2SC_INT_TXUR ATMEL_I2SC_SR_TXUR
161 static const struct regmap_config atmel_i2s_regmap_config = {
165 .max_register = ATMEL_I2SC_VERSION,
168 struct atmel_i2s_gck_param {
175 #define I2S_MCK_12M288 12288000UL
176 #define I2S_MCK_11M2896 11289600UL
178 /* mck = (32 * (imckfs+1) / (imckdiv+1)) * fs */
179 static const struct atmel_i2s_gck_param gck_params[] = {
180 /* mck = 12.288MHz */
181 { 8000, I2S_MCK_12M288, 0, 47}, /* mck = 1536 fs */
182 { 16000, I2S_MCK_12M288, 1, 47}, /* mck = 768 fs */
183 { 24000, I2S_MCK_12M288, 3, 63}, /* mck = 512 fs */
184 { 32000, I2S_MCK_12M288, 3, 47}, /* mck = 384 fs */
185 { 48000, I2S_MCK_12M288, 7, 63}, /* mck = 256 fs */
186 { 64000, I2S_MCK_12M288, 7, 47}, /* mck = 192 fs */
187 { 96000, I2S_MCK_12M288, 7, 31}, /* mck = 128 fs */
188 {192000, I2S_MCK_12M288, 7, 15}, /* mck = 64 fs */
190 /* mck = 11.2896MHz */
191 { 11025, I2S_MCK_11M2896, 1, 63}, /* mck = 1024 fs */
192 { 22050, I2S_MCK_11M2896, 3, 63}, /* mck = 512 fs */
193 { 44100, I2S_MCK_11M2896, 7, 63}, /* mck = 256 fs */
194 { 88200, I2S_MCK_11M2896, 7, 31}, /* mck = 128 fs */
195 {176400, I2S_MCK_11M2896, 7, 15}, /* mck = 64 fs */
198 struct atmel_i2s_dev;
200 struct atmel_i2s_caps {
201 int (*mck_init)(struct atmel_i2s_dev *, struct device_node *np);
204 struct atmel_i2s_dev {
206 struct regmap *regmap;
209 struct snd_dmaengine_dai_dma_data playback;
210 struct snd_dmaengine_dai_dma_data capture;
212 const struct atmel_i2s_gck_param *gck_param;
213 const struct atmel_i2s_caps *caps;
217 static irqreturn_t atmel_i2s_interrupt(int irq, void *dev_id)
219 struct atmel_i2s_dev *dev = dev_id;
220 unsigned int sr, imr, pending, ch, mask;
221 irqreturn_t ret = IRQ_NONE;
223 regmap_read(dev->regmap, ATMEL_I2SC_SR, &sr);
224 regmap_read(dev->regmap, ATMEL_I2SC_IMR, &imr);
230 if (pending & ATMEL_I2SC_INT_RXOR) {
231 mask = ATMEL_I2SC_SR_RXOR;
233 for (ch = 0; ch < ATMEL_I2SC_MAX_TDM_CHANNELS; ++ch) {
234 if (sr & ATMEL_I2SC_SR_RXORCH(ch)) {
235 mask |= ATMEL_I2SC_SR_RXORCH(ch);
237 "RX overrun on channel %d\n", ch);
240 regmap_write(dev->regmap, ATMEL_I2SC_SCR, mask);
244 if (pending & ATMEL_I2SC_INT_TXUR) {
245 mask = ATMEL_I2SC_SR_TXUR;
247 for (ch = 0; ch < ATMEL_I2SC_MAX_TDM_CHANNELS; ++ch) {
248 if (sr & ATMEL_I2SC_SR_TXURCH(ch)) {
249 mask |= ATMEL_I2SC_SR_TXURCH(ch);
251 "TX underrun on channel %d\n", ch);
254 regmap_write(dev->regmap, ATMEL_I2SC_SCR, mask);
261 #define ATMEL_I2S_RATES SNDRV_PCM_RATE_8000_192000
263 #define ATMEL_I2S_FORMATS (SNDRV_PCM_FMTBIT_S8 | \
264 SNDRV_PCM_FMTBIT_S16_LE | \
265 SNDRV_PCM_FMTBIT_S18_3LE | \
266 SNDRV_PCM_FMTBIT_S20_3LE | \
267 SNDRV_PCM_FMTBIT_S24_3LE | \
268 SNDRV_PCM_FMTBIT_S24_LE | \
269 SNDRV_PCM_FMTBIT_S32_LE)
271 static int atmel_i2s_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
273 struct atmel_i2s_dev *dev = snd_soc_dai_get_drvdata(dai);
279 static int atmel_i2s_prepare(struct snd_pcm_substream *substream,
280 struct snd_soc_dai *dai)
282 struct atmel_i2s_dev *dev = snd_soc_dai_get_drvdata(dai);
283 bool is_playback = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
284 unsigned int rhr, sr = 0;
287 regmap_read(dev->regmap, ATMEL_I2SC_SR, &sr);
288 if (sr & ATMEL_I2SC_SR_RXRDY) {
290 * The RX Ready flag should not be set. However if here,
291 * we flush (read) the Receive Holding Register to start
292 * from a clean state.
294 dev_dbg(dev->dev, "RXRDY is set\n");
295 regmap_read(dev->regmap, ATMEL_I2SC_RHR, &rhr);
302 static int atmel_i2s_get_gck_param(struct atmel_i2s_dev *dev, int fs)
307 dev_err(dev->dev, "cannot generate the I2S Master Clock\n");
312 * Find the best possible settings to generate the I2S Master Clock
313 * from the PLL Audio.
315 dev->gck_param = NULL;
317 for (i = 0; i < ARRAY_SIZE(gck_params); ++i) {
318 const struct atmel_i2s_gck_param *gck_param = &gck_params[i];
319 int val = abs(fs - gck_param->fs);
323 dev->gck_param = gck_param;
330 static int atmel_i2s_hw_params(struct snd_pcm_substream *substream,
331 struct snd_pcm_hw_params *params,
332 struct snd_soc_dai *dai)
334 struct atmel_i2s_dev *dev = snd_soc_dai_get_drvdata(dai);
335 bool is_playback = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
336 unsigned int mr = 0, mr_mask;
339 mr_mask = ATMEL_I2SC_MR_FORMAT_MASK | ATMEL_I2SC_MR_MODE_MASK |
340 ATMEL_I2SC_MR_DATALENGTH_MASK;
342 mr_mask |= ATMEL_I2SC_MR_TXMONO;
344 mr_mask |= ATMEL_I2SC_MR_RXMONO;
346 switch (dev->fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
347 case SND_SOC_DAIFMT_I2S:
348 mr |= ATMEL_I2SC_MR_FORMAT_I2S;
352 dev_err(dev->dev, "unsupported bus format\n");
356 switch (dev->fmt & SND_SOC_DAIFMT_MASTER_MASK) {
357 case SND_SOC_DAIFMT_CBS_CFS:
358 /* codec is slave, so cpu is master */
359 mr |= ATMEL_I2SC_MR_MODE_MASTER;
360 ret = atmel_i2s_get_gck_param(dev, params_rate(params));
365 case SND_SOC_DAIFMT_CBM_CFM:
366 /* codec is master, so cpu is slave */
367 mr |= ATMEL_I2SC_MR_MODE_SLAVE;
368 dev->gck_param = NULL;
372 dev_err(dev->dev, "unsupported master/slave mode\n");
376 switch (params_channels(params)) {
379 mr |= ATMEL_I2SC_MR_TXMONO;
381 mr |= ATMEL_I2SC_MR_RXMONO;
386 dev_err(dev->dev, "unsupported number of audio channels\n");
390 switch (params_format(params)) {
391 case SNDRV_PCM_FORMAT_S8:
392 mr |= ATMEL_I2SC_MR_DATALENGTH_8_BITS;
395 case SNDRV_PCM_FORMAT_S16_LE:
396 mr |= ATMEL_I2SC_MR_DATALENGTH_16_BITS;
399 case SNDRV_PCM_FORMAT_S18_3LE:
400 mr |= ATMEL_I2SC_MR_DATALENGTH_18_BITS | ATMEL_I2SC_MR_IWS;
403 case SNDRV_PCM_FORMAT_S20_3LE:
404 mr |= ATMEL_I2SC_MR_DATALENGTH_20_BITS | ATMEL_I2SC_MR_IWS;
407 case SNDRV_PCM_FORMAT_S24_3LE:
408 mr |= ATMEL_I2SC_MR_DATALENGTH_24_BITS | ATMEL_I2SC_MR_IWS;
411 case SNDRV_PCM_FORMAT_S24_LE:
412 mr |= ATMEL_I2SC_MR_DATALENGTH_24_BITS;
415 case SNDRV_PCM_FORMAT_S32_LE:
416 mr |= ATMEL_I2SC_MR_DATALENGTH_32_BITS;
420 dev_err(dev->dev, "unsupported size/endianness for audio samples\n");
424 return regmap_update_bits(dev->regmap, ATMEL_I2SC_MR, mr_mask, mr);
427 static int atmel_i2s_switch_mck_generator(struct atmel_i2s_dev *dev,
430 unsigned int mr, mr_mask;
431 unsigned long gclk_rate;
435 mr_mask = (ATMEL_I2SC_MR_IMCKDIV_MASK |
436 ATMEL_I2SC_MR_IMCKFS_MASK |
437 ATMEL_I2SC_MR_IMCKMODE_MASK);
440 /* Disable the I2S Master Clock generator. */
441 ret = regmap_write(dev->regmap, ATMEL_I2SC_CR,
442 ATMEL_I2SC_CR_CKDIS);
446 /* Reset the I2S Master Clock generator settings. */
447 ret = regmap_update_bits(dev->regmap, ATMEL_I2SC_MR,
452 /* Disable/unprepare the PMC generated clock. */
453 clk_disable_unprepare(dev->gclk);
461 gclk_rate = dev->gck_param->mck * (dev->gck_param->imckdiv + 1);
463 ret = clk_set_rate(dev->gclk, gclk_rate);
467 ret = clk_prepare_enable(dev->gclk);
471 /* Update the Mode Register to generate the I2S Master Clock. */
472 mr |= ATMEL_I2SC_MR_IMCKDIV(dev->gck_param->imckdiv);
473 mr |= ATMEL_I2SC_MR_IMCKFS(dev->gck_param->imckfs);
474 mr |= ATMEL_I2SC_MR_IMCKMODE_I2SMCK;
475 ret = regmap_update_bits(dev->regmap, ATMEL_I2SC_MR, mr_mask, mr);
479 /* Finally enable the I2S Master Clock generator. */
480 return regmap_write(dev->regmap, ATMEL_I2SC_CR,
484 static int atmel_i2s_trigger(struct snd_pcm_substream *substream, int cmd,
485 struct snd_soc_dai *dai)
487 struct atmel_i2s_dev *dev = snd_soc_dai_get_drvdata(dai);
488 bool is_playback = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
489 bool is_master, mck_enabled;
494 case SNDRV_PCM_TRIGGER_START:
495 case SNDRV_PCM_TRIGGER_RESUME:
496 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
497 cr = is_playback ? ATMEL_I2SC_CR_TXEN : ATMEL_I2SC_CR_RXEN;
500 case SNDRV_PCM_TRIGGER_STOP:
501 case SNDRV_PCM_TRIGGER_SUSPEND:
502 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
503 cr = is_playback ? ATMEL_I2SC_CR_TXDIS : ATMEL_I2SC_CR_RXDIS;
510 /* Read the Mode Register to retrieve the master/slave state. */
511 err = regmap_read(dev->regmap, ATMEL_I2SC_MR, &mr);
514 is_master = (mr & ATMEL_I2SC_MR_MODE_MASK) == ATMEL_I2SC_MR_MODE_MASTER;
516 /* If master starts, enable the audio clock. */
517 if (is_master && mck_enabled) {
518 if (!dev->clk_use_no) {
519 err = atmel_i2s_switch_mck_generator(dev, true);
526 err = regmap_write(dev->regmap, ATMEL_I2SC_CR, cr);
530 /* If master stops, disable the audio clock. */
531 if (is_master && !mck_enabled) {
532 if (dev->clk_use_no == 1) {
533 err = atmel_i2s_switch_mck_generator(dev, false);
543 static const struct snd_soc_dai_ops atmel_i2s_dai_ops = {
544 .prepare = atmel_i2s_prepare,
545 .trigger = atmel_i2s_trigger,
546 .hw_params = atmel_i2s_hw_params,
547 .set_fmt = atmel_i2s_set_dai_fmt,
550 static int atmel_i2s_dai_probe(struct snd_soc_dai *dai)
552 struct atmel_i2s_dev *dev = snd_soc_dai_get_drvdata(dai);
554 snd_soc_dai_init_dma_data(dai, &dev->playback, &dev->capture);
558 static struct snd_soc_dai_driver atmel_i2s_dai = {
559 .probe = atmel_i2s_dai_probe,
563 .rates = ATMEL_I2S_RATES,
564 .formats = ATMEL_I2S_FORMATS,
569 .rates = ATMEL_I2S_RATES,
570 .formats = ATMEL_I2S_FORMATS,
572 .ops = &atmel_i2s_dai_ops,
573 .symmetric_rates = 1,
576 static const struct snd_soc_component_driver atmel_i2s_component = {
580 static int atmel_i2s_sama5d2_mck_init(struct atmel_i2s_dev *dev,
581 struct device_node *np)
589 /* muxclk is optional, so we return error for probe defer only */
590 muxclk = devm_clk_get(dev->dev, "muxclk");
591 if (IS_ERR(muxclk)) {
592 err = PTR_ERR(muxclk);
593 if (err == -EPROBE_DEFER)
594 return -EPROBE_DEFER;
596 "failed to get the I2S clock control: %d\n", err);
600 return clk_set_parent(muxclk, dev->gclk);
603 static const struct atmel_i2s_caps atmel_i2s_sama5d2_caps = {
604 .mck_init = atmel_i2s_sama5d2_mck_init,
607 static const struct of_device_id atmel_i2s_dt_ids[] = {
609 .compatible = "atmel,sama5d2-i2s",
610 .data = (void *)&atmel_i2s_sama5d2_caps,
616 MODULE_DEVICE_TABLE(of, atmel_i2s_dt_ids);
618 static int atmel_i2s_probe(struct platform_device *pdev)
620 struct device_node *np = pdev->dev.of_node;
621 const struct of_device_id *match;
622 struct atmel_i2s_dev *dev;
623 struct resource *mem;
624 struct regmap *regmap;
628 unsigned int pcm_flags = 0;
629 unsigned int version;
631 /* Get memory for driver data. */
632 dev = devm_kzalloc(&pdev->dev, sizeof(*dev), GFP_KERNEL);
636 /* Get hardware capabilities. */
637 match = of_match_node(atmel_i2s_dt_ids, np);
639 dev->caps = match->data;
641 /* Map I/O registers. */
642 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
643 base = devm_ioremap_resource(&pdev->dev, mem);
645 return PTR_ERR(base);
647 regmap = devm_regmap_init_mmio(&pdev->dev, base,
648 &atmel_i2s_regmap_config);
650 return PTR_ERR(regmap);
653 irq = platform_get_irq(pdev, 0);
657 err = devm_request_irq(&pdev->dev, irq, atmel_i2s_interrupt, 0,
658 dev_name(&pdev->dev), dev);
662 /* Get the peripheral clock. */
663 dev->pclk = devm_clk_get(&pdev->dev, "pclk");
664 if (IS_ERR(dev->pclk)) {
665 err = PTR_ERR(dev->pclk);
667 "failed to get the peripheral clock: %d\n", err);
671 /* Get audio clock to generate the I2S Master Clock (I2S_MCK) */
672 dev->gclk = devm_clk_get(&pdev->dev, "gclk");
673 if (IS_ERR(dev->gclk)) {
674 if (PTR_ERR(dev->gclk) == -EPROBE_DEFER)
675 return -EPROBE_DEFER;
676 /* Master Mode not supported */
679 dev->dev = &pdev->dev;
680 dev->regmap = regmap;
681 platform_set_drvdata(pdev, dev);
683 /* Do hardware specific settings to initialize I2S_MCK generator */
684 if (dev->caps && dev->caps->mck_init) {
685 err = dev->caps->mck_init(dev, np);
690 /* Enable the peripheral clock. */
691 err = clk_prepare_enable(dev->pclk);
695 /* Get IP version. */
696 regmap_read(dev->regmap, ATMEL_I2SC_VERSION, &version);
697 dev_info(&pdev->dev, "hw version: %#x\n", version);
699 /* Enable error interrupts. */
700 regmap_write(dev->regmap, ATMEL_I2SC_IER,
701 ATMEL_I2SC_INT_RXOR | ATMEL_I2SC_INT_TXUR);
703 err = devm_snd_soc_register_component(&pdev->dev,
704 &atmel_i2s_component,
707 dev_err(&pdev->dev, "failed to register DAI: %d\n", err);
708 clk_disable_unprepare(dev->pclk);
712 /* Prepare DMA config. */
713 dev->playback.addr = (dma_addr_t)mem->start + ATMEL_I2SC_THR;
714 dev->playback.maxburst = 1;
715 dev->capture.addr = (dma_addr_t)mem->start + ATMEL_I2SC_RHR;
716 dev->capture.maxburst = 1;
718 if (of_property_match_string(np, "dma-names", "rx-tx") == 0)
719 pcm_flags |= SND_DMAENGINE_PCM_FLAG_HALF_DUPLEX;
720 err = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, pcm_flags);
722 dev_err(&pdev->dev, "failed to register PCM: %d\n", err);
723 clk_disable_unprepare(dev->pclk);
730 static int atmel_i2s_remove(struct platform_device *pdev)
732 struct atmel_i2s_dev *dev = platform_get_drvdata(pdev);
734 clk_disable_unprepare(dev->pclk);
739 static struct platform_driver atmel_i2s_driver = {
742 .of_match_table = of_match_ptr(atmel_i2s_dt_ids),
744 .probe = atmel_i2s_probe,
745 .remove = atmel_i2s_remove,
747 module_platform_driver(atmel_i2s_driver);
749 MODULE_DESCRIPTION("Atmel I2S Controller driver");
750 MODULE_AUTHOR("Cyrille Pitchen <cyrille.pitchen@atmel.com>");
751 MODULE_LICENSE("GPL v2");