1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * pata-legacy.c - Legacy port PATA/SATA controller driver.
4 * Copyright 2005/2006 Red Hat, all rights reserved.
6 * An ATA driver for the legacy ATA ports.
9 * Opti 82C465/82C611 support: Data sheets at opti-inc.com
11 * Promise 20230/20620:
12 * http://www.ryston.cz/petr/vlb/pdc20230b.html
13 * http://www.ryston.cz/petr/vlb/pdc20230c.html
14 * http://www.ryston.cz/petr/vlb/pdc20630.html
16 * http://www.ryston.cz/petr/vlb/qd6500.html
17 * http://www.ryston.cz/petr/vlb/qd6580.html
19 * QDI65x0 probe code based on drivers/ide/legacy/qd65xx.c
20 * Rewritten from the work of Colten Edwards <pje120@cs.usask.ca> by
21 * Samuel Thibault <samuel.thibault@ens-lyon.org>
23 * Unsupported but docs exist:
24 * Appian/Adaptec AIC25VL01/Cirrus Logic PD7220
26 * This driver handles legacy (that is "ISA/VLB side") IDE ports found
27 * on PC class systems. There are three hybrid devices that are exceptions
28 * The Cyrix 5510/5520 where a pre SFF ATA device is on the bridge and
29 * the MPIIX where the tuning is PCI side but the IDE is "ISA side".
31 * Specific support is included for the ht6560a/ht6560b/opti82c611a/
32 * opti82c465mv/promise 20230c/20630/qdi65x0/winbond83759A
34 * Support for the Winbond 83759A when operating in advanced mode.
35 * Multichip mode is not currently supported.
37 * Use the autospeed and pio_mask options with:
38 * Appian ADI/2 aka CLPD7220 or AIC25VL01.
39 * Use the jumpers, autospeed and set pio_mask to the mode on the jumpers with
40 * Goldstar GM82C711, PIC-1288A-125, UMC 82C871F, Winbond W83759,
41 * Winbond W83759A, Promise PDC20230-B
43 * For now use autospeed and pio_mask as above with the W83759A. This may
47 #include <linux/async.h>
48 #include <linux/kernel.h>
49 #include <linux/module.h>
50 #include <linux/pci.h>
51 #include <linux/init.h>
52 #include <linux/blkdev.h>
53 #include <linux/delay.h>
54 #include <scsi/scsi_host.h>
55 #include <linux/ata.h>
56 #include <linux/libata.h>
57 #include <linux/platform_device.h>
59 #define DRV_NAME "pata_legacy"
60 #define DRV_VERSION "0.6.5"
65 module_param(all, int, 0444);
66 MODULE_PARM_DESC(all, "Grab all legacy port devices, even if PCI(0=off, 1=on)");
78 QDI6580DP = 9, /* Dual channel mode is different */
90 struct platform_device *platform_dev;
99 unsigned long private;
102 struct legacy_controller {
104 struct ata_port_operations *ops;
105 unsigned int pio_mask;
108 int (*setup)(struct platform_device *, struct legacy_probe *probe,
109 struct legacy_data *data);
112 static int legacy_port[NR_HOST] = { 0x1f0, 0x170, 0x1e8, 0x168, 0x1e0, 0x160 };
114 static struct legacy_probe probe_list[NR_HOST];
115 static struct legacy_data legacy_data[NR_HOST];
116 static struct ata_host *legacy_host[NR_HOST];
117 static int nr_legacy_host;
120 static int probe_all; /* Set to check all ISA port ranges */
121 static int ht6560a; /* HT 6560A on primary 1, second 2, both 3 */
122 static int ht6560b; /* HT 6560A on primary 1, second 2, both 3 */
123 static int opti82c611a; /* Opti82c611A on primary 1, sec 2, both 3 */
124 static int opti82c46x; /* Opti 82c465MV present(pri/sec autodetect) */
125 static int autospeed; /* Chip present which snoops speed changes */
126 static int pio_mask = ATA_PIO4; /* PIO range for autospeed devices */
127 static int iordy_mask = 0xFFFFFFFF; /* Use iordy if available */
129 /* Set to probe QDI controllers */
130 #ifdef CONFIG_PATA_QDI_MODULE
136 #ifdef CONFIG_PATA_WINBOND_VLB_MODULE
137 static int winbond = 1; /* Set to probe Winbond controllers,
138 give I/O port if non standard */
140 static int winbond; /* Set to probe Winbond controllers,
141 give I/O port if non standard */
145 * legacy_probe_add - Add interface to probe list
146 * @port: Controller port
148 * @type: Controller type
149 * @private: Controller specific info
151 * Add an entry into the probe list for ATA controllers. This is used
152 * to add the default ISA slots and then to build up the table
153 * further according to other ISA/VLB/Weird device scans
155 * An I/O port list is used to keep ordering stable and sane, as we
156 * don't have any good way to talk about ordering otherwise
159 static int legacy_probe_add(unsigned long port, unsigned int irq,
160 enum controller type, unsigned long private)
162 struct legacy_probe *lp = &probe_list[0];
164 struct legacy_probe *free = NULL;
166 for (i = 0; i < NR_HOST; i++) {
167 if (lp->port == 0 && free == NULL)
169 /* Matching port, or the correct slot for ordering */
170 if (lp->port == port || legacy_port[i] == port) {
177 printk(KERN_ERR "pata_legacy: Too many interfaces.\n");
180 /* Fill in the entry for later probing */
184 free->private = private;
190 * legacy_set_mode - mode setting
192 * @unused: Device that failed when error is returned
194 * Use a non standard set_mode function. We don't want to be tuned.
196 * The BIOS configured everything. Our job is not to fiddle. Just use
197 * whatever PIO the hardware is using and leave it at that. When we
198 * get some kind of nice user driven API for control then we can
199 * expand on this as per hdparm in the base kernel.
202 static int legacy_set_mode(struct ata_link *link, struct ata_device **unused)
204 struct ata_device *dev;
206 ata_for_each_dev(dev, link, ENABLED) {
207 ata_dev_info(dev, "configured for PIO\n");
208 dev->pio_mode = XFER_PIO_0;
209 dev->xfer_mode = XFER_PIO_0;
210 dev->xfer_shift = ATA_SHIFT_PIO;
211 dev->flags |= ATA_DFLAG_PIO;
216 static struct scsi_host_template legacy_sht = {
217 ATA_PIO_SHT(DRV_NAME),
220 static const struct ata_port_operations legacy_base_port_ops = {
221 .inherits = &ata_sff_port_ops,
222 .cable_detect = ata_cable_40wire,
226 * These ops are used if the user indicates the hardware
227 * snoops the commands to decide on the mode and handles the
228 * mode selection "magically" itself. Several legacy controllers
229 * do this. The mode range can be set if it is not 0x1F by setting
233 static struct ata_port_operations simple_port_ops = {
234 .inherits = &legacy_base_port_ops,
235 .sff_data_xfer = ata_sff_data_xfer32,
238 static struct ata_port_operations legacy_port_ops = {
239 .inherits = &legacy_base_port_ops,
240 .sff_data_xfer = ata_sff_data_xfer32,
241 .set_mode = legacy_set_mode,
245 * Promise 20230C and 20620 support
247 * This controller supports PIO0 to PIO2. We set PIO timings
248 * conservatively to allow for 50MHz Vesa Local Bus. The 20620 DMA
249 * support is weird being DMA to controller and PIO'd to the host
253 static void pdc20230_set_piomode(struct ata_port *ap, struct ata_device *adev)
256 int pio = adev->pio_mode - XFER_PIO_0;
260 /* Safe as UP only. Force I/Os to occur together */
262 local_irq_save(flags);
264 /* Unlock the control interface */
267 outb(inb(0x1F2) | 0x80, 0x1F2);
274 while ((inb(0x1F2) & 0x80) && --tries);
276 local_irq_restore(flags);
278 outb(inb(0x1F4) & 0x07, 0x1F4);
281 rt &= 0x07 << (3 * adev->devno);
283 rt |= (1 + 3 * pio) << (3 * adev->devno);
286 outb(inb(0x1F2) | 0x01, 0x1F2);
292 static unsigned int pdc_data_xfer_vlb(struct ata_queued_cmd *qc,
293 unsigned char *buf, unsigned int buflen, int rw)
295 struct ata_device *dev = qc->dev;
296 struct ata_port *ap = dev->link->ap;
297 int slop = buflen & 3;
299 /* 32bit I/O capable *and* we need to write a whole number of dwords */
300 if (ata_id_has_dword_io(dev->id) && (slop == 0 || slop == 3)
301 && (ap->pflags & ATA_PFLAG_PIO32)) {
304 local_irq_save(flags);
306 /* Perform the 32bit I/O synchronization sequence */
307 ioread8(ap->ioaddr.nsect_addr);
308 ioread8(ap->ioaddr.nsect_addr);
309 ioread8(ap->ioaddr.nsect_addr);
313 ioread32_rep(ap->ioaddr.data_addr, buf, buflen >> 2);
315 iowrite32_rep(ap->ioaddr.data_addr, buf, buflen >> 2);
317 if (unlikely(slop)) {
321 pad = cpu_to_le32(ioread32(ap->ioaddr.data_addr));
322 memcpy(buf + buflen - slop, &pad, slop);
324 memcpy(&pad, buf + buflen - slop, slop);
325 iowrite32(le32_to_cpu(pad), ap->ioaddr.data_addr);
329 local_irq_restore(flags);
331 buflen = ata_sff_data_xfer32(qc, buf, buflen, rw);
336 static struct ata_port_operations pdc20230_port_ops = {
337 .inherits = &legacy_base_port_ops,
338 .set_piomode = pdc20230_set_piomode,
339 .sff_data_xfer = pdc_data_xfer_vlb,
343 * Holtek 6560A support
345 * This controller supports PIO0 to PIO2 (no IORDY even though higher
346 * timings can be loaded).
349 static void ht6560a_set_piomode(struct ata_port *ap, struct ata_device *adev)
354 /* Get the timing data in cycles. For now play safe at 50Mhz */
355 ata_timing_compute(adev, adev->pio_mode, &t, 20000, 1000);
357 active = clamp_val(t.active, 2, 15);
358 recover = clamp_val(t.recover, 4, 15);
365 iowrite8(recover << 4 | active, ap->ioaddr.device_addr);
366 ioread8(ap->ioaddr.status_addr);
369 static struct ata_port_operations ht6560a_port_ops = {
370 .inherits = &legacy_base_port_ops,
371 .set_piomode = ht6560a_set_piomode,
375 * Holtek 6560B support
377 * This controller supports PIO0 to PIO4. We honour the BIOS/jumper FIFO
378 * setting unless we see an ATAPI device in which case we force it off.
380 * FIXME: need to implement 2nd channel support.
383 static void ht6560b_set_piomode(struct ata_port *ap, struct ata_device *adev)
388 /* Get the timing data in cycles. For now play safe at 50Mhz */
389 ata_timing_compute(adev, adev->pio_mode, &t, 20000, 1000);
391 active = clamp_val(t.active, 2, 15);
392 recover = clamp_val(t.recover, 2, 16) & 0x0F;
399 iowrite8(recover << 4 | active, ap->ioaddr.device_addr);
401 if (adev->class != ATA_DEV_ATA) {
402 u8 rconf = inb(0x3E6);
408 ioread8(ap->ioaddr.status_addr);
411 static struct ata_port_operations ht6560b_port_ops = {
412 .inherits = &legacy_base_port_ops,
413 .set_piomode = ht6560b_set_piomode,
417 * Opti core chipset helpers
421 * opti_syscfg - read OPTI chipset configuration
422 * @reg: Configuration register to read
424 * Returns the value of an OPTI system board configuration register.
427 static u8 opti_syscfg(u8 reg)
432 /* Uniprocessor chipset and must force cycles adjancent */
433 local_irq_save(flags);
436 local_irq_restore(flags);
443 * This controller supports PIO0 to PIO3.
446 static void opti82c611a_set_piomode(struct ata_port *ap,
447 struct ata_device *adev)
449 u8 active, recover, setup;
451 struct ata_device *pair = ata_dev_pair(adev);
453 int khz[4] = { 50000, 40000, 33000, 25000 };
456 /* Enter configuration mode */
457 ioread16(ap->ioaddr.error_addr);
458 ioread16(ap->ioaddr.error_addr);
459 iowrite8(3, ap->ioaddr.nsect_addr);
461 /* Read VLB clock strapping */
462 clock = 1000000000 / khz[ioread8(ap->ioaddr.lbah_addr) & 0x03];
464 /* Get the timing data in cycles */
465 ata_timing_compute(adev, adev->pio_mode, &t, clock, 1000);
467 /* Setup timing is shared */
469 struct ata_timing tp;
470 ata_timing_compute(pair, pair->pio_mode, &tp, clock, 1000);
472 ata_timing_merge(&t, &tp, &t, ATA_TIMING_SETUP);
475 active = clamp_val(t.active, 2, 17) - 2;
476 recover = clamp_val(t.recover, 1, 16) - 1;
477 setup = clamp_val(t.setup, 1, 4) - 1;
479 /* Select the right timing bank for write timing */
480 rc = ioread8(ap->ioaddr.lbal_addr);
482 rc |= (adev->devno << 7);
483 iowrite8(rc, ap->ioaddr.lbal_addr);
485 /* Write the timings */
486 iowrite8(active << 4 | recover, ap->ioaddr.error_addr);
488 /* Select the right bank for read timings, also
489 load the shared timings for address */
490 rc = ioread8(ap->ioaddr.device_addr);
492 rc |= adev->devno; /* Index select */
493 rc |= (setup << 4) | 0x04;
494 iowrite8(rc, ap->ioaddr.device_addr);
496 /* Load the read timings */
497 iowrite8(active << 4 | recover, ap->ioaddr.data_addr);
499 /* Ensure the timing register mode is right */
500 rc = ioread8(ap->ioaddr.lbal_addr);
503 iowrite8(rc, ap->ioaddr.lbal_addr);
505 /* Exit command mode */
506 iowrite8(0x83, ap->ioaddr.nsect_addr);
510 static struct ata_port_operations opti82c611a_port_ops = {
511 .inherits = &legacy_base_port_ops,
512 .set_piomode = opti82c611a_set_piomode,
518 * This controller supports PIO0 to PIO3. Unlike the 611A the MVB
519 * version is dual channel but doesn't have a lot of unique registers.
522 static void opti82c46x_set_piomode(struct ata_port *ap, struct ata_device *adev)
524 u8 active, recover, setup;
526 struct ata_device *pair = ata_dev_pair(adev);
528 int khz[4] = { 50000, 40000, 33000, 25000 };
533 sysclk = (opti_syscfg(0xAC) & 0xC0) >> 6; /* BIOS set */
535 /* Enter configuration mode */
536 ioread16(ap->ioaddr.error_addr);
537 ioread16(ap->ioaddr.error_addr);
538 iowrite8(3, ap->ioaddr.nsect_addr);
540 /* Read VLB clock strapping */
541 clock = 1000000000 / khz[sysclk];
543 /* Get the timing data in cycles */
544 ata_timing_compute(adev, adev->pio_mode, &t, clock, 1000);
546 /* Setup timing is shared */
548 struct ata_timing tp;
549 ata_timing_compute(pair, pair->pio_mode, &tp, clock, 1000);
551 ata_timing_merge(&t, &tp, &t, ATA_TIMING_SETUP);
554 active = clamp_val(t.active, 2, 17) - 2;
555 recover = clamp_val(t.recover, 1, 16) - 1;
556 setup = clamp_val(t.setup, 1, 4) - 1;
558 /* Select the right timing bank for write timing */
559 rc = ioread8(ap->ioaddr.lbal_addr);
561 rc |= (adev->devno << 7);
562 iowrite8(rc, ap->ioaddr.lbal_addr);
564 /* Write the timings */
565 iowrite8(active << 4 | recover, ap->ioaddr.error_addr);
567 /* Select the right bank for read timings, also
568 load the shared timings for address */
569 rc = ioread8(ap->ioaddr.device_addr);
571 rc |= adev->devno; /* Index select */
572 rc |= (setup << 4) | 0x04;
573 iowrite8(rc, ap->ioaddr.device_addr);
575 /* Load the read timings */
576 iowrite8(active << 4 | recover, ap->ioaddr.data_addr);
578 /* Ensure the timing register mode is right */
579 rc = ioread8(ap->ioaddr.lbal_addr);
582 iowrite8(rc, ap->ioaddr.lbal_addr);
584 /* Exit command mode */
585 iowrite8(0x83, ap->ioaddr.nsect_addr);
587 /* We need to know this for quad device on the MVB */
588 ap->host->private_data = ap;
592 * opt82c465mv_qc_issue - command issue
593 * @qc: command pending
595 * Called when the libata layer is about to issue a command. We wrap
596 * this interface so that we can load the correct ATA timings. The
597 * MVB has a single set of timing registers and these are shared
598 * across channels. As there are two registers we really ought to
599 * track the last two used values as a sort of register window. For
600 * now we just reload on a channel switch. On the single channel
601 * setup this condition never fires so we do nothing extra.
603 * FIXME: dual channel needs ->serialize support
606 static unsigned int opti82c46x_qc_issue(struct ata_queued_cmd *qc)
608 struct ata_port *ap = qc->ap;
609 struct ata_device *adev = qc->dev;
611 /* If timings are set and for the wrong channel (2nd test is
612 due to a libata shortcoming and will eventually go I hope) */
613 if (ap->host->private_data != ap->host
614 && ap->host->private_data != NULL)
615 opti82c46x_set_piomode(ap, adev);
617 return ata_sff_qc_issue(qc);
620 static struct ata_port_operations opti82c46x_port_ops = {
621 .inherits = &legacy_base_port_ops,
622 .set_piomode = opti82c46x_set_piomode,
623 .qc_issue = opti82c46x_qc_issue,
627 * qdi65x0_set_piomode - PIO setup for QDI65x0
631 * In single channel mode the 6580 has one clock per device and we can
632 * avoid the requirement to clock switch. We also have to load the timing
633 * into the right clock according to whether we are master or slave.
635 * In dual channel mode the 6580 has one clock per channel and we have
636 * to software clockswitch in qc_issue.
639 static void qdi65x0_set_piomode(struct ata_port *ap, struct ata_device *adev)
642 struct legacy_data *ld_qdi = ap->host->private_data;
643 int active, recovery;
646 /* Get the timing data in cycles */
647 ata_timing_compute(adev, adev->pio_mode, &t, 30303, 1000);
650 active = 8 - clamp_val(t.active, 1, 8);
651 recovery = 18 - clamp_val(t.recover, 3, 18);
653 active = 9 - clamp_val(t.active, 2, 9);
654 recovery = 15 - clamp_val(t.recover, 0, 15);
656 timing = (recovery << 4) | active | 0x08;
657 ld_qdi->clock[adev->devno] = timing;
659 if (ld_qdi->type == QDI6580)
660 outb(timing, ld_qdi->timing + 2 * adev->devno);
662 outb(timing, ld_qdi->timing + 2 * ap->port_no);
665 if (ld_qdi->type != QDI6500 && adev->class != ATA_DEV_ATA)
666 outb(0x5F, (ld_qdi->timing & 0xFFF0) + 3);
670 * qdi_qc_issue - command issue
671 * @qc: command pending
673 * Called when the libata layer is about to issue a command. We wrap
674 * this interface so that we can load the correct ATA timings.
677 static unsigned int qdi_qc_issue(struct ata_queued_cmd *qc)
679 struct ata_port *ap = qc->ap;
680 struct ata_device *adev = qc->dev;
681 struct legacy_data *ld_qdi = ap->host->private_data;
683 if (ld_qdi->clock[adev->devno] != ld_qdi->last) {
684 if (adev->pio_mode) {
685 ld_qdi->last = ld_qdi->clock[adev->devno];
686 outb(ld_qdi->clock[adev->devno], ld_qdi->timing +
690 return ata_sff_qc_issue(qc);
693 static unsigned int vlb32_data_xfer(struct ata_queued_cmd *qc,
695 unsigned int buflen, int rw)
697 struct ata_device *adev = qc->dev;
698 struct ata_port *ap = adev->link->ap;
699 int slop = buflen & 3;
701 if (ata_id_has_dword_io(adev->id) && (slop == 0 || slop == 3)
702 && (ap->pflags & ATA_PFLAG_PIO32)) {
704 iowrite32_rep(ap->ioaddr.data_addr, buf, buflen >> 2);
706 ioread32_rep(ap->ioaddr.data_addr, buf, buflen >> 2);
708 if (unlikely(slop)) {
712 memcpy(&pad, buf + buflen - slop, slop);
713 iowrite32(le32_to_cpu(pad), ap->ioaddr.data_addr);
715 pad = cpu_to_le32(ioread32(ap->ioaddr.data_addr));
716 memcpy(buf + buflen - slop, &pad, slop);
719 return (buflen + 3) & ~3;
721 return ata_sff_data_xfer(qc, buf, buflen, rw);
724 static int qdi_port(struct platform_device *dev,
725 struct legacy_probe *lp, struct legacy_data *ld)
727 if (devm_request_region(&dev->dev, lp->private, 4, "qdi") == NULL)
729 ld->timing = lp->private;
733 static struct ata_port_operations qdi6500_port_ops = {
734 .inherits = &legacy_base_port_ops,
735 .set_piomode = qdi65x0_set_piomode,
736 .qc_issue = qdi_qc_issue,
737 .sff_data_xfer = vlb32_data_xfer,
740 static struct ata_port_operations qdi6580_port_ops = {
741 .inherits = &legacy_base_port_ops,
742 .set_piomode = qdi65x0_set_piomode,
743 .sff_data_xfer = vlb32_data_xfer,
746 static struct ata_port_operations qdi6580dp_port_ops = {
747 .inherits = &legacy_base_port_ops,
748 .set_piomode = qdi65x0_set_piomode,
749 .qc_issue = qdi_qc_issue,
750 .sff_data_xfer = vlb32_data_xfer,
753 static DEFINE_SPINLOCK(winbond_lock);
755 static void winbond_writecfg(unsigned long port, u8 reg, u8 val)
758 spin_lock_irqsave(&winbond_lock, flags);
759 outb(reg, port + 0x01);
760 outb(val, port + 0x02);
761 spin_unlock_irqrestore(&winbond_lock, flags);
764 static u8 winbond_readcfg(unsigned long port, u8 reg)
769 spin_lock_irqsave(&winbond_lock, flags);
770 outb(reg, port + 0x01);
771 val = inb(port + 0x02);
772 spin_unlock_irqrestore(&winbond_lock, flags);
777 static void winbond_set_piomode(struct ata_port *ap, struct ata_device *adev)
780 struct legacy_data *ld_winbond = ap->host->private_data;
781 int active, recovery;
783 int timing = 0x88 + (ap->port_no * 4) + (adev->devno * 2);
785 reg = winbond_readcfg(ld_winbond->timing, 0x81);
787 /* Get the timing data in cycles */
788 if (reg & 0x40) /* Fast VLB bus, assume 50MHz */
789 ata_timing_compute(adev, adev->pio_mode, &t, 20000, 1000);
791 ata_timing_compute(adev, adev->pio_mode, &t, 30303, 1000);
793 active = (clamp_val(t.active, 3, 17) - 1) & 0x0F;
794 recovery = (clamp_val(t.recover, 1, 15) + 1) & 0x0F;
795 timing = (active << 4) | recovery;
796 winbond_writecfg(ld_winbond->timing, timing, reg);
798 /* Load the setup timing */
801 if (adev->class != ATA_DEV_ATA)
802 reg |= 0x08; /* FIFO off */
803 if (!ata_pio_need_iordy(adev))
804 reg |= 0x02; /* IORDY off */
805 reg |= (clamp_val(t.setup, 0, 3) << 6);
806 winbond_writecfg(ld_winbond->timing, timing + 1, reg);
809 static int winbond_port(struct platform_device *dev,
810 struct legacy_probe *lp, struct legacy_data *ld)
812 if (devm_request_region(&dev->dev, lp->private, 4, "winbond") == NULL)
814 ld->timing = lp->private;
818 static struct ata_port_operations winbond_port_ops = {
819 .inherits = &legacy_base_port_ops,
820 .set_piomode = winbond_set_piomode,
821 .sff_data_xfer = vlb32_data_xfer,
824 static struct legacy_controller controllers[] = {
825 {"BIOS", &legacy_port_ops, ATA_PIO4,
826 ATA_FLAG_NO_IORDY, 0, NULL },
827 {"Snooping", &simple_port_ops, ATA_PIO4,
829 {"PDC20230", &pdc20230_port_ops, ATA_PIO2,
831 ATA_PFLAG_PIO32 | ATA_PFLAG_PIO32CHANGE, NULL },
832 {"HT6560A", &ht6560a_port_ops, ATA_PIO2,
833 ATA_FLAG_NO_IORDY, 0, NULL },
834 {"HT6560B", &ht6560b_port_ops, ATA_PIO4,
835 ATA_FLAG_NO_IORDY, 0, NULL },
836 {"OPTI82C611A", &opti82c611a_port_ops, ATA_PIO3,
838 {"OPTI82C46X", &opti82c46x_port_ops, ATA_PIO3,
840 {"QDI6500", &qdi6500_port_ops, ATA_PIO2,
842 ATA_PFLAG_PIO32 | ATA_PFLAG_PIO32CHANGE, qdi_port },
843 {"QDI6580", &qdi6580_port_ops, ATA_PIO4,
844 0, ATA_PFLAG_PIO32 | ATA_PFLAG_PIO32CHANGE, qdi_port },
845 {"QDI6580DP", &qdi6580dp_port_ops, ATA_PIO4,
846 0, ATA_PFLAG_PIO32 | ATA_PFLAG_PIO32CHANGE, qdi_port },
847 {"W83759A", &winbond_port_ops, ATA_PIO4,
848 0, ATA_PFLAG_PIO32 | ATA_PFLAG_PIO32CHANGE,
853 * probe_chip_type - Discover controller
854 * @probe: Probe entry to check
856 * Probe an ATA port and identify the type of controller. We don't
857 * check if the controller appears to be driveless at this point.
860 static __init int probe_chip_type(struct legacy_probe *probe)
862 int mask = 1 << probe->slot;
864 if (winbond && (probe->port == 0x1F0 || probe->port == 0x170)) {
865 u8 reg = winbond_readcfg(winbond, 0x81);
866 reg |= 0x80; /* jumpered mode off */
867 winbond_writecfg(winbond, 0x81, reg);
868 reg = winbond_readcfg(winbond, 0x83);
869 reg |= 0xF0; /* local control */
870 winbond_writecfg(winbond, 0x83, reg);
871 reg = winbond_readcfg(winbond, 0x85);
872 reg |= 0xF0; /* programmable timing */
873 winbond_writecfg(winbond, 0x85, reg);
875 reg = winbond_readcfg(winbond, 0x81);
880 if (probe->port == 0x1F0) {
882 local_irq_save(flags);
884 outb(inb(0x1F2) | 0x80, 0x1F2);
892 if ((inb(0x1F2) & 0x80) == 0) {
893 /* PDC20230c or 20630 ? */
894 printk(KERN_INFO "PDC20230-C/20630 VLB ATA controller"
898 local_irq_restore(flags);
904 if (inb(0x1F2) == 0x00)
905 printk(KERN_INFO "PDC20230-B VLB ATA "
906 "controller detected.\n");
907 local_irq_restore(flags);
916 if (opti82c611a & mask)
918 if (opti82c46x & mask)
920 if (autospeed & mask)
927 * legacy_init_one - attach a legacy interface
930 * Register an ISA bus IDE interface. Such interfaces are PIO and we
931 * assume do not support IRQ sharing.
934 static __init int legacy_init_one(struct legacy_probe *probe)
936 struct legacy_controller *controller = &controllers[probe->type];
937 int pio_modes = controller->pio_mask;
938 unsigned long io = probe->port;
939 u32 mask = (1 << probe->slot);
940 struct ata_port_operations *ops = controller->ops;
941 struct legacy_data *ld = &legacy_data[probe->slot];
942 struct ata_host *host = NULL;
944 struct platform_device *pdev;
945 struct ata_device *dev;
946 void __iomem *io_addr, *ctrl_addr;
947 u32 iordy = (iordy_mask & mask) ? 0: ATA_FLAG_NO_IORDY;
950 iordy |= controller->flags;
952 pdev = platform_device_register_simple(DRV_NAME, probe->slot, NULL, 0);
954 return PTR_ERR(pdev);
957 if (devm_request_region(&pdev->dev, io, 8, "pata_legacy") == NULL ||
958 devm_request_region(&pdev->dev, io + 0x0206, 1,
959 "pata_legacy") == NULL)
963 io_addr = devm_ioport_map(&pdev->dev, io, 8);
964 ctrl_addr = devm_ioport_map(&pdev->dev, io + 0x0206, 1);
965 if (!io_addr || !ctrl_addr)
967 ld->type = probe->type;
968 if (controller->setup)
969 if (controller->setup(pdev, probe, ld) < 0)
971 host = ata_host_alloc(&pdev->dev, 1);
977 ap->pio_mask = pio_modes;
978 ap->flags |= ATA_FLAG_SLAVE_POSS | iordy;
979 ap->pflags |= controller->pflags;
980 ap->ioaddr.cmd_addr = io_addr;
981 ap->ioaddr.altstatus_addr = ctrl_addr;
982 ap->ioaddr.ctl_addr = ctrl_addr;
983 ata_sff_std_ports(&ap->ioaddr);
984 ap->host->private_data = ld;
986 ata_port_desc(ap, "cmd 0x%lx ctl 0x%lx", io, io + 0x0206);
988 ret = ata_host_activate(host, probe->irq, ata_sff_interrupt, 0,
992 async_synchronize_full();
993 ld->platform_dev = pdev;
995 /* Nothing found means we drop the port as its probably not there */
998 ata_for_each_dev(dev, &ap->link, ALL) {
999 if (!ata_dev_absent(dev)) {
1000 legacy_host[probe->slot] = host;
1001 ld->platform_dev = pdev;
1005 ata_host_detach(host);
1007 platform_device_unregister(pdev);
1012 * legacy_check_special_cases - ATA special cases
1013 * @p: PCI device to check
1014 * @master: set this if we find an ATA master
1015 * @master: set this if we find an ATA secondary
1017 * A small number of vendors implemented early PCI ATA interfaces
1018 * on bridge logic without the ATA interface being PCI visible.
1019 * Where we have a matching PCI driver we must skip the relevant
1020 * device here. If we don't know about it then the legacy driver
1021 * is the right driver anyway.
1024 static void __init legacy_check_special_cases(struct pci_dev *p, int *primary,
1027 /* Cyrix CS5510 pre SFF MWDMA ATA on the bridge */
1028 if (p->vendor == 0x1078 && p->device == 0x0000) {
1029 *primary = *secondary = 1;
1032 /* Cyrix CS5520 pre SFF MWDMA ATA on the bridge */
1033 if (p->vendor == 0x1078 && p->device == 0x0002) {
1034 *primary = *secondary = 1;
1037 /* Intel MPIIX - PIO ATA on non PCI side of bridge */
1038 if (p->vendor == 0x8086 && p->device == 0x1234) {
1040 pci_read_config_word(p, 0x6C, &r);
1042 /* ATA port enabled */
1052 static __init void probe_opti_vlb(void)
1054 /* If an OPTI 82C46X is present find out where the channels are */
1055 static const char *optis[4] = {
1060 u8 ctrl = (opti_syscfg(0x30) & 0xC0) >> 6;
1062 opti82c46x = 3; /* Assume master and slave first */
1063 printk(KERN_INFO DRV_NAME ": Opti 82C46%s chipset support.\n",
1066 chans = (opti_syscfg(0x3F) & 0x20) ? 2 : 1;
1067 ctrl = opti_syscfg(0xAC);
1068 /* Check enabled and this port is the 465MV port. On the
1069 MVB we may have two channels */
1072 legacy_probe_add(0x1F0, 14, OPTI46X, 0);
1073 legacy_probe_add(0x170, 15, OPTI46X, 0);
1076 legacy_probe_add(0x170, 15, OPTI46X, 0);
1078 legacy_probe_add(0x1F0, 14, OPTI46X, 0);
1080 legacy_probe_add(0x1F0, 14, OPTI46X, 0);
1083 static __init void qdi65_identify_port(u8 r, u8 res, unsigned long port)
1085 static const unsigned long ide_port[2] = { 0x170, 0x1F0 };
1086 /* Check card type */
1087 if ((r & 0xF0) == 0xC0) {
1088 /* QD6500: single channel */
1092 legacy_probe_add(ide_port[r & 0x01], 14 + (r & 0x01),
1095 if (((r & 0xF0) == 0xA0) || (r & 0xF0) == 0x50) {
1096 /* QD6580: dual channel */
1097 if (!request_region(port + 2 , 2, "pata_qdi")) {
1098 release_region(port, 2);
1101 res = inb(port + 3);
1102 /* Single channel mode ? */
1104 legacy_probe_add(ide_port[r & 0x01], 14 + (r & 0x01),
1106 else { /* Dual channel mode */
1107 legacy_probe_add(0x1F0, 14, QDI6580DP, port);
1108 /* port + 0x02, r & 0x04 */
1109 legacy_probe_add(0x170, 15, QDI6580DP, port + 2);
1111 release_region(port + 2, 2);
1115 static __init void probe_qdi_vlb(void)
1117 unsigned long flags;
1118 static const unsigned long qd_port[2] = { 0x30, 0xB0 };
1122 * Check each possible QD65xx base address
1125 for (i = 0; i < 2; i++) {
1126 unsigned long port = qd_port[i];
1130 if (request_region(port, 2, "pata_qdi")) {
1131 /* Check for a card */
1132 local_irq_save(flags);
1133 /* I have no h/w that needs this delay but it
1134 is present in the historic code */
1143 local_irq_restore(flags);
1147 release_region(port, 2);
1150 /* Passes the presence test */
1153 /* Check port agrees with port set */
1154 if ((r & 2) >> 1 == i)
1155 qdi65_identify_port(r, res, port);
1156 release_region(port, 2);
1162 * legacy_init - attach legacy interfaces
1164 * Attach legacy IDE interfaces by scanning the usual IRQ/port suspects.
1165 * Right now we do not scan the ide0 and ide1 address but should do so
1166 * for non PCI systems or systems with no PCI IDE legacy mode devices.
1167 * If you fix that note there are special cases to consider like VLB
1168 * drivers and CS5510/20.
1171 static __init int legacy_init(void)
1177 int pci_present = 0;
1178 struct legacy_probe *pl = &probe_list[0];
1181 struct pci_dev *p = NULL;
1183 for_each_pci_dev(p) {
1185 /* Check for any overlap of the system ATA mappings. Native
1186 mode controllers stuck on these addresses or some devices
1187 in 'raid' mode won't be found by the storage class test */
1188 for (r = 0; r < 6; r++) {
1189 if (pci_resource_start(p, r) == 0x1f0)
1191 if (pci_resource_start(p, r) == 0x170)
1194 /* Check for special cases */
1195 legacy_check_special_cases(p, &primary, &secondary);
1197 /* If PCI bus is present then don't probe for tertiary
1203 winbond = 0x130; /* Default port, alt is 1B0 */
1205 if (primary == 0 || all)
1206 legacy_probe_add(0x1F0, 14, UNKNOWN, 0);
1207 if (secondary == 0 || all)
1208 legacy_probe_add(0x170, 15, UNKNOWN, 0);
1210 if (probe_all || !pci_present) {
1211 /* ISA/VLB extra ports */
1212 legacy_probe_add(0x1E8, 11, UNKNOWN, 0);
1213 legacy_probe_add(0x168, 10, UNKNOWN, 0);
1214 legacy_probe_add(0x1E0, 8, UNKNOWN, 0);
1215 legacy_probe_add(0x160, 12, UNKNOWN, 0);
1223 for (i = 0; i < NR_HOST; i++, pl++) {
1226 if (pl->type == UNKNOWN)
1227 pl->type = probe_chip_type(pl);
1229 if (legacy_init_one(pl) == 0)
1237 static __exit void legacy_exit(void)
1241 for (i = 0; i < nr_legacy_host; i++) {
1242 struct legacy_data *ld = &legacy_data[i];
1243 ata_host_detach(legacy_host[i]);
1244 platform_device_unregister(ld->platform_dev);
1248 MODULE_AUTHOR("Alan Cox");
1249 MODULE_DESCRIPTION("low-level driver for legacy ATA");
1250 MODULE_LICENSE("GPL");
1251 MODULE_VERSION(DRV_VERSION);
1252 MODULE_ALIAS("pata_qdi");
1253 MODULE_ALIAS("pata_winbond");
1255 module_param(probe_all, int, 0);
1256 module_param(autospeed, int, 0);
1257 module_param(ht6560a, int, 0);
1258 module_param(ht6560b, int, 0);
1259 module_param(opti82c611a, int, 0);
1260 module_param(opti82c46x, int, 0);
1261 module_param(qdi, int, 0);
1262 module_param(winbond, int, 0);
1263 module_param(pio_mask, int, 0);
1264 module_param(iordy_mask, int, 0);
1266 module_init(legacy_init);
1267 module_exit(legacy_exit);