2 * include/at86rf230.h - AT86RF230/AT86RF231 protocol and register definitions
4 * Written 2008-2011 by Werner Almesberger
5 * Copyright 2008-2011 Werner Almesberger
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
18 AT86RF230_REG_WRITE = 0xc0, /* 11... */
19 AT86RF230_REG_READ = 0x80, /* 10... */
20 AT86RF230_BUF_WRITE = 0x60, /* 011... */
21 AT86RF230_BUF_READ = 0x20, /* 001... */
22 AT86RF230_SRAM_WRITE = 0x40, /* 010... */
23 AT86RF230_SRAM_READ = 0x00 /* 000... */
26 #define MAX_PSDU 127 /* octets, see AT86RF230 manual section 8.1 */
30 /* --- Registers ----------------------------------------------------------- */
33 REG_TRX_STATUS = 0x01,
35 REG_TRX_CTRL_0 = 0x03,
37 REG_TRX_CTRL_1 = 0x04, /* 231 only */
39 REG_PHY_TX_PWR = 0x05,
41 REG_PHY_ED_LEVEL = 0x07,
42 REG_PHY_CC_CCA = 0x08,
45 REG_RX_CTRL = 0x0a, /* 231 only */
46 REG_SFD_VALUE = 0x0b, /* 231 only */
47 REG_TRX_CTRL_2 = 0x0c, /* 231 only */
48 REG_ANT_DIV = 0x0d, /* 231 only */
51 REG_IRQ_STATUS = 0x0f,
56 REG_RX_SYN = 0x15, /* 231 only */
57 REG_XAH_CTRL_1 = 0x17, /* 231 only */
58 REG_FTN_CTRL = 0x18, /* 231 only */
63 REG_VERSION_NUM = 0x1d,
66 REG_SHORT_ADDR_0 = 0x20,
67 REG_SHORT_ADDR_1 = 0x21,
70 REG_IEEE_ADDR_0 = 0x24,
71 REG_IEEE_ADDR_1 = 0x25,
72 REG_IEEE_ADDR_2 = 0x26,
73 REG_IEEE_ADDR_3 = 0x27,
74 REG_IEEE_ADDR_4 = 0x28,
75 REG_IEEE_ADDR_5 = 0x29,
76 REG_IEEE_ADDR_6 = 0x2a,
77 REG_IEEE_ADDR_7 = 0x2b,
79 REG_XAH_CTRL_0 = 0x2c, /* XAH_CTRL in 230 */
80 REG_CSMA_SEED_0 = 0x2d,
81 REG_CSMA_SEED_1 = 0x2e,
82 REG_CSMA_BE = 0x2f, /* 231 only */
85 REG_CONT_TX_1 = 0x3d, /* 230 only */
88 /* --- TRX_STATUS --- ------------------------------------------------------ */
90 #define CCA_DONE (1 << 7)
91 #define CCA_STATUS (1 << 6)
93 #define TRX_STATUS_SHIFT 0
94 #define TRX_STATUS_MASK 0x1f
97 TRX_STATUS_P_ON = 0x00, /* reset default */
98 TRX_STATUS_BUSY_RX = 0x01,
99 TRX_STATUS_BUSY_TX = 0x02,
100 TRX_STATUS_RX_ON = 0x06,
101 TRX_STATUS_TRX_OFF = 0x08,
102 TRX_STATUS_PLL_ON = 0x09,
103 TRX_STATUS_SLEEP = 0x0f,
104 TRX_STATUS_BUSY_RX_AACK = 0x11,
105 TRX_STATUS_BUSY_TX_ARET = 0x12,
106 TRX_STATUS_RX_AACK_ON = 0x16,
107 TRX_STATUS_TX_ARET_ON = 0x19,
108 TRX_STATUS_RX_ON_NOCLK = 0x1c,
109 TRX_STATUS_RX_AACK_ON_NOCLK = 0x1d,
110 TRX_STATUS_BUSY_RX_AACK_NOCLK = 0x1e,
111 TRX_STATUS_TRANSITION = 0x1f /* ..._IN_PROGRESS */
114 /* --- TRX_STATE ----------------------------------------------------------- */
116 #define TRAC_STATUS_SHIFT 5
117 #define TRAC_STATUS_MASK 7
120 TRAC_STATUS_SUCCESS = 0, /* reset default */
121 TRAC_STATUS_SUCCESS_DATA_PENDING = 1,
122 TRAC_STATUS_SUCCESS_WAIT_FOR_ACK = 2, /* 231 only */
123 TRAC_STATUS_CHANNEL_ACCESS_FAILURE = 3,
124 TRAC_STATUS_NO_ACK = 5,
125 TRAC_STATUS_INVALID = 7
128 #define TRX_CMD_SHIFT 0
129 #define TRX_CMD_MASK 0x1f
132 TRX_CMD_NOP = 0x00, /* reset default */
133 TRX_CMD_TX_START = 0x02,
134 TRX_CMD_FORCE_TRX_OFF = 0x03,
135 TRX_CMD_FORCE_PLL_ON = 0x04, /* 231 only */
136 TRX_CMD_RX_ON = 0x06,
137 TRX_CMD_TRX_OFF = 0x08,
138 TRX_CMD_PLL_ON = 0x09,
139 TRX_CMD_RX_AACK_ON = 0x16,
140 TRX_CMD_TX_ARET_ON = 0x19,
143 /* --- TRX_CTRL_0 ---------------------------------------------------------- */
145 #define PAD_IO_SHIFT 6
146 #define PAD_IO_MASK 3
149 PAD_IO_2mA, /* reset default */
155 #define PAD_IO_CLKM_SHIFT 4
156 #define PAD_IO_CLKM_MASK 3
160 PAD_IO_CLKM_4mA, /* reset default */
165 #define CLKM_SHA_SEL (1 << 3)
167 #define CLKM_CTRL_SHIFT 0
168 #define CLKM_CTRL_MASK 7
172 CLKM_CTRL_1MHz = 1, /* reset default */
179 /* --- TRX_CTRL_1 (231 only) ----------------------------------------------- */
181 #define PA_EXT_EN (1 << 7)
182 #define IRQ_2_EXT_EN (1 << 6)
183 #define TX_AUTO_CRC_ON (1 << 5) /* 231 location */
184 #define RX_BL_CTRL (1 << 4)
186 #define SPI_CMD_MODE_SHIFT 2
187 #define SPI_CMD_MODE_MASK 3
190 SPI_CMD_MODE_EMPTY = 0, /* reset default */
191 SPI_CMD_MODE_TRX_STATUS = 1,
192 SPI_CMD_MODE_PHY_RSSI = 2,
193 SPI_CMD_MODE_IRQ_STATUS = 3,
196 #define IRQ_MASK_MODE (1 << 1)
197 #define IRQ_POLARITY (1 << 0)
199 /* --- PHY_TX_PWR ---------------------------------------------------------- */
201 #define TX_AUTO_CRC_ON_230 (1 << 7) /* 230 location */
203 #define PA_BUF_LT_SHIFT 6
204 #define PA_BUF_LT_MASK 3
206 #define PA_LT_SHIFT 4
209 #define TX_PWR_SHIFT 0
210 #define TX_PWR_MASK 0x0f
212 /* --- PHY_RSSI ------------------------------------------------------------ */
214 #define RX_CRC_VALID (1 << 7)
216 #define RND_VALUE_SHIFT 5 /* 231 only */
217 #define RND_VALUE_MASK 3
220 #define RSSI_MASK 0x1f
222 /* --- PHY_CC_CCA ---------------------------------------------------------- */
224 #define CCA_REQUEST (1 << 7)
226 #define CCA_MODE_SHIFT 5
227 #define CCA_MODE_MASK 3
230 CCA_MODE_CARRIER_OR_ENERGY = 0, /* 231 only */
231 CCA_MODE_ENERGY = 1, /* reset default */
232 CCA_MODE_CARRIER = 2,
233 CCA_MODE_CARRIER_AND_ENERGY = 3
236 #define CHANNEL_SHIFT 0
237 #define CHANNEL_MASK 0x1f
239 /* --- CCA_THRES ----------------------------------------------------------- */
241 #define CCA_ED_THRES_SHIFT 0
242 #define CCA_ED_THRES_MASK 0x0f
244 /* --- RX_CTRL (231 only) -------------------------------------------------- */
246 #define PDT_THRES_SHIFT 0
247 #define PDT_THRES_MASK 0x0f
250 PDT_THRES_DEFAULT = 0x07, /* reset default */
251 PDT_THRES_DIVERSITY = 0x03,
254 /* --- TRX_CTRL_2 (231 only) ----------------------------------------------- */
256 #define RX_SAFE_MODE (1 << 7)
258 #define OQPSK_DATA_RATE_SHIFT 0
259 #define OQPSK_DATA_RATE_MASK 3
262 OQPSK_DATA_RATE_250 = 0, /* reset default */
263 OQPSK_DATA_RATE_500 = 1,
264 OQPSK_DATA_RATE_1000 = 2,
265 OQPSK_DATA_RATE_2000 = 3
268 /* --- ANT_DIV (231 only) -------------------------------------------------- */
270 #define ANT_SEL (1 << 7)
271 #define ANT_DIV_EN (1 << 3)
272 #define ANT_EXT_SW_EN (1 << 2)
274 #define ANT_CTRL_SHIFT 0
275 #define ANT_CTRL_MASK 3
280 ANT_CTRL_NODIV = 3, /* reset default */
283 /* --- IRQ_MASK/IRQ_STATUS ------------------------------------------------- */
286 IRQ_PLL_LOCK = 1 << 0,
287 IRQ_PLL_UNLOCK = 1 << 1,
288 IRQ_RX_START = 1 << 2,
289 IRQ_TRX_END = 1 << 3,
290 IRQ_CCA_ED_DONE = 1 << 4, /* 231 only */
291 IRQ_AMI = 1 << 5, /* 231 only */
296 /* --- VREG_CTRL ----------------------------------------------------------- */
298 #define AVREG_EXT (1 << 7)
299 #define AVDD_OK (1 << 6)
300 #define DVREG_EXT (1 << 3)
301 #define DVDD_OK (1 << 2)
303 /* --- BATMON -------------------------------------------------------------- */
305 #define BATMON_OK (1 << 5)
306 #define BATMON_HR (1 << 4)
308 #define BATMON_VTH_SHIFT 0
309 #define BATMON_VTH_MASK 0x0f
311 /* --- XOSC_CTRL ----------------------------------------------------------- */
313 #define XTAL_MODE_SHIFT 4
314 #define XTAL_MODE_MASK 0x0f
317 XTAL_MODE_OFF = 0x0, /* 230 only */
319 XTAL_MODE_INT = 0xf /* reset default */
322 #define XTAL_TRIM_SHIFT 4
323 #define XTAL_TRIM_MASK 0x0f
325 /* --- RX_SYN (231 only) --------------------------------------------------- */
327 #define RX_PDT_DIS (1 << 7)
329 #define RX_PDT_LEVEL_SHIFT 0
330 #define RX_PDT_LEVEL_MASK 0xf
332 /* --- XAH_CTRL_1 (231 only) ----------------------------------------------- */
334 #define AACK_FLTR_RES_FT (1 << 5)
335 #define AACK_UPLD_RES_FT (1 << 4)
336 #define AACK_ACK_TIME (1 << 2)
337 #define AACK_PROM_MODE (1 << 1)
339 /* --- FTN_CTRL (231 only) ------------------------------------------------- */
341 #define FTN_START (1 << 7)
343 /* --- PLL_CF -------------------------------------------------------------- */
345 #define PLL_CF_START (1 << 7)
347 /* --- PLL_DCU ------------------------------------------------------------- */
349 #define PLL_DCU_START (1 << 7)
351 /* --- XAH_CTRL_0 (XAH_CTRL in 230) ---------------------------------------- */
353 #define MAX_FRAME_RETRIES_SHIFT 4
354 #define MAX_FRAME_RETRIES_MASK 0x0f
356 #define MAX_CSMA_RETRIES_SHIFT 1
357 #define MAX_CSMA_RETRIES_MASK 0x07
359 #define SLOTTED_OPERATION (1 << 0) /* 231 only */
361 /* --- CSMA_SEED_1 --------------------------------------------------------- */
363 #define MIN_BE_SHIFT_230 6 /* 230 location */
364 #define MIN_BE_MASK_230 3
366 #define AACK_FVN_MODE_SHIFT 6 /* 231 only */
367 #define AACK_FVN_MODE_MASK 3
371 AACK_FVN_MODE_01 = 1, /* reset default */
372 AACK_FVN_MODE_012 = 2,
373 AACK_FVN_MODE_ANY = 3
376 #define AACK_SET_PD (1 << 5)
377 #define AACK_DIS_ACK (1 << 4) /* 231 only */
378 #define I_AM_COORD (1 << 3)
380 #define CSMA_SEED_1_SHIFT 0
381 #define CSMA_SEED_1_MASK 7
383 /* --- CSMA_BE ------------------------------------------------------------- */
385 #define MAX_BE_SHIFT 4
386 #define MAX_BE_MASK 0x0f
388 #define MIN_BE_SHIFT 0 /* 231 location */
389 #define MIN_BE_MASK 0x0f
391 /* --- REG_CONT_TX_0 ------------------------------------------------------- */
393 #define CONT_TX_MAGIC 0x0f
395 /* --- REG_CONT_TX_1 (230 only) -------------------------------------------- */
397 #define CONT_TX_MOD 0x00 /* modulated */
398 #define CONT_TX_M2M 0x10 /* f_CH-2 MHz */
399 #define CONT_TX_M500K 0x80 /* f_CH-0.5 MHz */
400 #define CONT_TX_P500K 0xc0 /* f_CH+0.5 MHz */
402 #endif /* !AT86RF230_H */