1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 #ifndef _ASM_POWERPC_IO_H
3 #define _ASM_POWERPC_IO_H
6 #define ARCH_HAS_IOREMAP_WC
8 #define ARCH_HAS_IOREMAP_WT
14 /* Check of existence of legacy devices */
15 extern int check_legacy_ioport(unsigned long base_port);
16 #define I8042_DATA_REG 0x60
17 #define FDC_BASE 0x3f0
19 #if defined(CONFIG_PPC64) && defined(CONFIG_PCI)
20 extern struct pci_dev *isa_bridge_pcidev;
22 * has legacy ISA devices ?
24 #define arch_has_dev_port() (isa_bridge_pcidev != NULL || isa_io_special)
27 #include <linux/device.h>
28 #include <linux/compiler.h>
31 #include <asm/byteorder.h>
32 #include <asm/synch.h>
33 #include <asm/delay.h>
34 #include <asm/mmiowb.h>
37 #define SIO_CONFIG_RA 0x398
38 #define SIO_CONFIG_RD 0x399
40 /* 32 bits uses slightly different variables for the various IO
41 * bases. Most of this file only uses _IO_BASE though which we
42 * define properly based on the platform
46 #define _ISA_MEM_BASE 0
47 #define PCI_DRAM_OFFSET 0
48 #elif defined(CONFIG_PPC32)
49 #define _IO_BASE isa_io_base
50 #define _ISA_MEM_BASE isa_mem_base
51 #define PCI_DRAM_OFFSET pci_dram_offset
53 #define _IO_BASE pci_io_base
54 #define _ISA_MEM_BASE isa_mem_base
55 #define PCI_DRAM_OFFSET 0
58 extern unsigned long isa_io_base;
59 extern unsigned long pci_io_base;
60 extern unsigned long pci_dram_offset;
62 extern resource_size_t isa_mem_base;
64 /* Boolean set by platform if PIO accesses are suppored while _IO_BASE
65 * is not set or addresses cannot be translated to MMIO. This is typically
66 * set when the platform supports "special" PIO accesses via a non memory
67 * mapped mechanism, and allows things like the early udbg UART code to
70 extern bool isa_io_special;
73 #if defined(CONFIG_PPC_INDIRECT_PIO) || defined(CONFIG_PPC_INDIRECT_MMIO)
74 #error CONFIG_PPC_INDIRECT_{PIO,MMIO} are not yet supported on 32 bits
80 * Low level MMIO accessors
82 * This provides the non-bus specific accessors to MMIO. Those are PowerPC
83 * specific and thus shouldn't be used in generic code. The accessors
86 * in_8, in_le16, in_be16, in_le32, in_be32, in_le64, in_be64
87 * out_8, out_le16, out_be16, out_le32, out_be32, out_le64, out_be64
88 * _insb, _insw_ns, _insl_ns, _outsb, _outsw_ns, _outsl_ns
90 * Those operate directly on a kernel virtual address. Note that the prototype
91 * for the out_* accessors has the arguments in opposite order from the usual
92 * linux PCI accessors. Unlike those, they take the address first and the value
95 * Note: I might drop the _ns suffix on the stream operations soon as it is
96 * simply normal for stream operations to not swap in the first place.
100 /* -mprefixed can generate offsets beyond range, fall back hack */
101 #ifdef CONFIG_PPC_KERNEL_PREFIXED
102 #define DEF_MMIO_IN_X(name, size, insn) \
103 static inline u##size name(const volatile u##size __iomem *addr) \
106 __asm__ __volatile__("sync;"#insn" %0,0,%1;twi 0,%0,0;isync" \
107 : "=r" (ret) : "r" (addr) : "memory"); \
111 #define DEF_MMIO_OUT_X(name, size, insn) \
112 static inline void name(volatile u##size __iomem *addr, u##size val) \
114 __asm__ __volatile__("sync;"#insn" %1,0,%0" \
115 : : "r" (addr), "r" (val) : "memory"); \
116 mmiowb_set_pending(); \
119 #define DEF_MMIO_IN_D(name, size, insn) \
120 static inline u##size name(const volatile u##size __iomem *addr) \
123 __asm__ __volatile__("sync;"#insn" %0,0(%1);twi 0,%0,0;isync"\
124 : "=r" (ret) : "b" (addr) : "memory"); \
128 #define DEF_MMIO_OUT_D(name, size, insn) \
129 static inline void name(volatile u##size __iomem *addr, u##size val) \
131 __asm__ __volatile__("sync;"#insn" %1,0(%0)" \
132 : : "b" (addr), "r" (val) : "memory"); \
133 mmiowb_set_pending(); \
136 #define DEF_MMIO_IN_X(name, size, insn) \
137 static inline u##size name(const volatile u##size __iomem *addr) \
140 __asm__ __volatile__("sync;"#insn" %0,%y1;twi 0,%0,0;isync" \
141 : "=r" (ret) : "Z" (*addr) : "memory"); \
145 #define DEF_MMIO_OUT_X(name, size, insn) \
146 static inline void name(volatile u##size __iomem *addr, u##size val) \
148 __asm__ __volatile__("sync;"#insn" %1,%y0" \
149 : "=Z" (*addr) : "r" (val) : "memory"); \
150 mmiowb_set_pending(); \
153 #define DEF_MMIO_IN_D(name, size, insn) \
154 static inline u##size name(const volatile u##size __iomem *addr) \
157 __asm__ __volatile__("sync;"#insn"%U1%X1 %0,%1;twi 0,%0,0;isync"\
158 : "=r" (ret) : "m<>" (*addr) : "memory"); \
162 #define DEF_MMIO_OUT_D(name, size, insn) \
163 static inline void name(volatile u##size __iomem *addr, u##size val) \
165 __asm__ __volatile__("sync;"#insn"%U0%X0 %1,%0" \
166 : "=m<>" (*addr) : "r" (val) : "memory"); \
167 mmiowb_set_pending(); \
171 DEF_MMIO_IN_D(in_8, 8, lbz);
172 DEF_MMIO_OUT_D(out_8, 8, stb);
174 #ifdef __BIG_ENDIAN__
175 DEF_MMIO_IN_D(in_be16, 16, lhz);
176 DEF_MMIO_IN_D(in_be32, 32, lwz);
177 DEF_MMIO_IN_X(in_le16, 16, lhbrx);
178 DEF_MMIO_IN_X(in_le32, 32, lwbrx);
180 DEF_MMIO_OUT_D(out_be16, 16, sth);
181 DEF_MMIO_OUT_D(out_be32, 32, stw);
182 DEF_MMIO_OUT_X(out_le16, 16, sthbrx);
183 DEF_MMIO_OUT_X(out_le32, 32, stwbrx);
185 DEF_MMIO_IN_X(in_be16, 16, lhbrx);
186 DEF_MMIO_IN_X(in_be32, 32, lwbrx);
187 DEF_MMIO_IN_D(in_le16, 16, lhz);
188 DEF_MMIO_IN_D(in_le32, 32, lwz);
190 DEF_MMIO_OUT_X(out_be16, 16, sthbrx);
191 DEF_MMIO_OUT_X(out_be32, 32, stwbrx);
192 DEF_MMIO_OUT_D(out_le16, 16, sth);
193 DEF_MMIO_OUT_D(out_le32, 32, stw);
195 #endif /* __BIG_ENDIAN */
199 #ifdef __BIG_ENDIAN__
200 DEF_MMIO_OUT_D(out_be64, 64, std);
201 DEF_MMIO_IN_D(in_be64, 64, ld);
203 /* There is no asm instructions for 64 bits reverse loads and stores */
204 static inline u64 in_le64(const volatile u64 __iomem *addr)
206 return swab64(in_be64(addr));
209 static inline void out_le64(volatile u64 __iomem *addr, u64 val)
211 out_be64(addr, swab64(val));
214 DEF_MMIO_OUT_D(out_le64, 64, std);
215 DEF_MMIO_IN_D(in_le64, 64, ld);
217 /* There is no asm instructions for 64 bits reverse loads and stores */
218 static inline u64 in_be64(const volatile u64 __iomem *addr)
220 return swab64(in_le64(addr));
223 static inline void out_be64(volatile u64 __iomem *addr, u64 val)
225 out_le64(addr, swab64(val));
229 #endif /* __powerpc64__ */
232 * Low level IO stream instructions are defined out of line for now
234 extern void _insb(const volatile u8 __iomem *addr, void *buf, long count);
235 extern void _outsb(volatile u8 __iomem *addr,const void *buf,long count);
236 extern void _insw_ns(const volatile u16 __iomem *addr, void *buf, long count);
237 extern void _outsw_ns(volatile u16 __iomem *addr, const void *buf, long count);
238 extern void _insl_ns(const volatile u32 __iomem *addr, void *buf, long count);
239 extern void _outsl_ns(volatile u32 __iomem *addr, const void *buf, long count);
241 /* The _ns naming is historical and will be removed. For now, just #define
242 * the non _ns equivalent names
244 #define _insw _insw_ns
245 #define _insl _insl_ns
246 #define _outsw _outsw_ns
247 #define _outsl _outsl_ns
251 * memset_io, memcpy_toio, memcpy_fromio base implementations are out of line
254 extern void _memset_io(volatile void __iomem *addr, int c, unsigned long n);
255 extern void _memcpy_fromio(void *dest, const volatile void __iomem *src,
257 extern void _memcpy_toio(volatile void __iomem *dest, const void *src,
262 * PCI and standard ISA accessors
264 * Those are globally defined linux accessors for devices on PCI or ISA
265 * busses. They follow the Linux defined semantics. The current implementation
266 * for PowerPC is as close as possible to the x86 version of these, and thus
267 * provides fairly heavy weight barriers for the non-raw versions
269 * In addition, they support a hook mechanism when CONFIG_PPC_INDIRECT_MMIO
270 * or CONFIG_PPC_INDIRECT_PIO are set allowing the platform to provide its
271 * own implementation of some or all of the accessors.
275 * Include the EEH definitions when EEH is enabled only so they don't get
276 * in the way when building for 32 bits
282 /* Shortcut to the MMIO argument pointer */
283 #define PCI_IO_ADDR volatile void __iomem *
285 /* Indirect IO address tokens:
287 * When CONFIG_PPC_INDIRECT_MMIO is set, the platform can provide hooks
288 * on all MMIOs. (Note that this is all 64 bits only for now)
290 * To help platforms who may need to differentiate MMIO addresses in
291 * their hooks, a bitfield is reserved for use by the platform near the
292 * top of MMIO addresses (not PIO, those have to cope the hard way).
294 * The highest address in the kernel virtual space are:
296 * d0003fffffffffff # with Hash MMU
297 * c00fffffffffffff # with Radix MMU
299 * The top 4 bits are reserved as the region ID on hash, leaving us 8 bits
300 * that can be used for the field.
302 * The direct IO mapping operations will then mask off those bits
303 * before doing the actual access, though that only happen when
304 * CONFIG_PPC_INDIRECT_MMIO is set, thus be careful when you use that
307 * For PIO, there is a separate CONFIG_PPC_INDIRECT_PIO which makes
308 * all PIO functions call through a hook.
311 #ifdef CONFIG_PPC_INDIRECT_MMIO
312 #define PCI_IO_IND_TOKEN_SHIFT 52
313 #define PCI_IO_IND_TOKEN_MASK (0xfful << PCI_IO_IND_TOKEN_SHIFT)
314 #define PCI_FIX_ADDR(addr) \
315 ((PCI_IO_ADDR)(((unsigned long)(addr)) & ~PCI_IO_IND_TOKEN_MASK))
316 #define PCI_GET_ADDR_TOKEN(addr) \
317 (((unsigned long)(addr) & PCI_IO_IND_TOKEN_MASK) >> \
318 PCI_IO_IND_TOKEN_SHIFT)
319 #define PCI_SET_ADDR_TOKEN(addr, token) \
321 unsigned long __a = (unsigned long)(addr); \
322 __a &= ~PCI_IO_IND_TOKEN_MASK; \
323 __a |= ((unsigned long)(token)) << PCI_IO_IND_TOKEN_SHIFT; \
324 (addr) = (void __iomem *)__a; \
327 #define PCI_FIX_ADDR(addr) (addr)
332 * Non ordered and non-swapping "raw" accessors
335 static inline unsigned char __raw_readb(const volatile void __iomem *addr)
337 return *(volatile unsigned char __force *)PCI_FIX_ADDR(addr);
339 #define __raw_readb __raw_readb
341 static inline unsigned short __raw_readw(const volatile void __iomem *addr)
343 return *(volatile unsigned short __force *)PCI_FIX_ADDR(addr);
345 #define __raw_readw __raw_readw
347 static inline unsigned int __raw_readl(const volatile void __iomem *addr)
349 return *(volatile unsigned int __force *)PCI_FIX_ADDR(addr);
351 #define __raw_readl __raw_readl
353 static inline void __raw_writeb(unsigned char v, volatile void __iomem *addr)
355 *(volatile unsigned char __force *)PCI_FIX_ADDR(addr) = v;
357 #define __raw_writeb __raw_writeb
359 static inline void __raw_writew(unsigned short v, volatile void __iomem *addr)
361 *(volatile unsigned short __force *)PCI_FIX_ADDR(addr) = v;
363 #define __raw_writew __raw_writew
365 static inline void __raw_writel(unsigned int v, volatile void __iomem *addr)
367 *(volatile unsigned int __force *)PCI_FIX_ADDR(addr) = v;
369 #define __raw_writel __raw_writel
372 static inline unsigned long __raw_readq(const volatile void __iomem *addr)
374 return *(volatile unsigned long __force *)PCI_FIX_ADDR(addr);
376 #define __raw_readq __raw_readq
378 static inline void __raw_writeq(unsigned long v, volatile void __iomem *addr)
380 *(volatile unsigned long __force *)PCI_FIX_ADDR(addr) = v;
382 #define __raw_writeq __raw_writeq
384 static inline void __raw_writeq_be(unsigned long v, volatile void __iomem *addr)
386 __raw_writeq((__force unsigned long)cpu_to_be64(v), addr);
388 #define __raw_writeq_be __raw_writeq_be
391 * Real mode versions of the above. Those instructions are only supposed
392 * to be used in hypervisor real mode as per the architecture spec.
394 static inline void __raw_rm_writeb(u8 val, volatile void __iomem *paddr)
396 __asm__ __volatile__(".machine push; \
400 : : "r" (val), "r" (paddr) : "memory");
403 static inline void __raw_rm_writew(u16 val, volatile void __iomem *paddr)
405 __asm__ __volatile__(".machine push; \
409 : : "r" (val), "r" (paddr) : "memory");
412 static inline void __raw_rm_writel(u32 val, volatile void __iomem *paddr)
414 __asm__ __volatile__(".machine push; \
418 : : "r" (val), "r" (paddr) : "memory");
421 static inline void __raw_rm_writeq(u64 val, volatile void __iomem *paddr)
423 __asm__ __volatile__(".machine push; \
427 : : "r" (val), "r" (paddr) : "memory");
430 static inline void __raw_rm_writeq_be(u64 val, volatile void __iomem *paddr)
432 __raw_rm_writeq((__force u64)cpu_to_be64(val), paddr);
435 static inline u8 __raw_rm_readb(volatile void __iomem *paddr)
438 __asm__ __volatile__(".machine push; \
442 : "=r" (ret) : "r" (paddr) : "memory");
446 static inline u16 __raw_rm_readw(volatile void __iomem *paddr)
449 __asm__ __volatile__(".machine push; \
453 : "=r" (ret) : "r" (paddr) : "memory");
457 static inline u32 __raw_rm_readl(volatile void __iomem *paddr)
460 __asm__ __volatile__(".machine push; \
464 : "=r" (ret) : "r" (paddr) : "memory");
468 static inline u64 __raw_rm_readq(volatile void __iomem *paddr)
471 __asm__ __volatile__(".machine push; \
475 : "=r" (ret) : "r" (paddr) : "memory");
478 #endif /* __powerpc64__ */
482 * PCI PIO and MMIO accessors.
485 * On 32 bits, PIO operations have a recovery mechanism in case they trigger
486 * machine checks (which they occasionally do when probing non existing
487 * IO ports on some platforms, like PowerMac and 8xx).
488 * I always found it to be of dubious reliability and I am tempted to get
489 * rid of it one of these days. So if you think it's important to keep it,
490 * please voice up asap. We never had it for 64 bits and I do not intend
496 #define __do_in_asm(name, op) \
497 static inline unsigned int name(unsigned int port) \
500 __asm__ __volatile__( \
502 "0:" op " %0,0,%1\n" \
507 ".section .fixup,\"ax\"\n" \
516 : "r" (port + _IO_BASE) \
521 #define __do_out_asm(name, op) \
522 static inline void name(unsigned int val, unsigned int port) \
524 __asm__ __volatile__( \
526 "0:" op " %0,0,%1\n" \
531 : : "r" (val), "r" (port + _IO_BASE) \
535 __do_in_asm(_rec_inb, "lbzx")
536 __do_in_asm(_rec_inw, "lhbrx")
537 __do_in_asm(_rec_inl, "lwbrx")
538 __do_out_asm(_rec_outb, "stbx")
539 __do_out_asm(_rec_outw, "sthbrx")
540 __do_out_asm(_rec_outl, "stwbrx")
542 #endif /* CONFIG_PPC32 */
544 /* The "__do_*" operations below provide the actual "base" implementation
545 * for each of the defined accessors. Some of them use the out_* functions
546 * directly, some of them still use EEH, though we might change that in the
547 * future. Those macros below provide the necessary argument swapping and
548 * handling of the IO base for PIO.
550 * They are themselves used by the macros that define the actual accessors
551 * and can be used by the hooks if any.
553 * Note that PIO operations are always defined in terms of their corresonding
554 * MMIO operations. That allows platforms like iSeries who want to modify the
555 * behaviour of both to only hook on the MMIO version and get both. It's also
556 * possible to hook directly at the toplevel PIO operation if they have to
557 * be handled differently
559 #define __do_writeb(val, addr) out_8(PCI_FIX_ADDR(addr), val)
560 #define __do_writew(val, addr) out_le16(PCI_FIX_ADDR(addr), val)
561 #define __do_writel(val, addr) out_le32(PCI_FIX_ADDR(addr), val)
562 #define __do_writeq(val, addr) out_le64(PCI_FIX_ADDR(addr), val)
563 #define __do_writew_be(val, addr) out_be16(PCI_FIX_ADDR(addr), val)
564 #define __do_writel_be(val, addr) out_be32(PCI_FIX_ADDR(addr), val)
565 #define __do_writeq_be(val, addr) out_be64(PCI_FIX_ADDR(addr), val)
568 #define __do_readb(addr) eeh_readb(PCI_FIX_ADDR(addr))
569 #define __do_readw(addr) eeh_readw(PCI_FIX_ADDR(addr))
570 #define __do_readl(addr) eeh_readl(PCI_FIX_ADDR(addr))
571 #define __do_readq(addr) eeh_readq(PCI_FIX_ADDR(addr))
572 #define __do_readw_be(addr) eeh_readw_be(PCI_FIX_ADDR(addr))
573 #define __do_readl_be(addr) eeh_readl_be(PCI_FIX_ADDR(addr))
574 #define __do_readq_be(addr) eeh_readq_be(PCI_FIX_ADDR(addr))
575 #else /* CONFIG_EEH */
576 #define __do_readb(addr) in_8(PCI_FIX_ADDR(addr))
577 #define __do_readw(addr) in_le16(PCI_FIX_ADDR(addr))
578 #define __do_readl(addr) in_le32(PCI_FIX_ADDR(addr))
579 #define __do_readq(addr) in_le64(PCI_FIX_ADDR(addr))
580 #define __do_readw_be(addr) in_be16(PCI_FIX_ADDR(addr))
581 #define __do_readl_be(addr) in_be32(PCI_FIX_ADDR(addr))
582 #define __do_readq_be(addr) in_be64(PCI_FIX_ADDR(addr))
583 #endif /* !defined(CONFIG_EEH) */
586 #define __do_outb(val, port) _rec_outb(val, port)
587 #define __do_outw(val, port) _rec_outw(val, port)
588 #define __do_outl(val, port) _rec_outl(val, port)
589 #define __do_inb(port) _rec_inb(port)
590 #define __do_inw(port) _rec_inw(port)
591 #define __do_inl(port) _rec_inl(port)
592 #else /* CONFIG_PPC32 */
593 #define __do_outb(val, port) writeb(val,(PCI_IO_ADDR)_IO_BASE+port);
594 #define __do_outw(val, port) writew(val,(PCI_IO_ADDR)_IO_BASE+port);
595 #define __do_outl(val, port) writel(val,(PCI_IO_ADDR)_IO_BASE+port);
596 #define __do_inb(port) readb((PCI_IO_ADDR)_IO_BASE + port);
597 #define __do_inw(port) readw((PCI_IO_ADDR)_IO_BASE + port);
598 #define __do_inl(port) readl((PCI_IO_ADDR)_IO_BASE + port);
599 #endif /* !CONFIG_PPC32 */
602 #define __do_readsb(a, b, n) eeh_readsb(PCI_FIX_ADDR(a), (b), (n))
603 #define __do_readsw(a, b, n) eeh_readsw(PCI_FIX_ADDR(a), (b), (n))
604 #define __do_readsl(a, b, n) eeh_readsl(PCI_FIX_ADDR(a), (b), (n))
605 #else /* CONFIG_EEH */
606 #define __do_readsb(a, b, n) _insb(PCI_FIX_ADDR(a), (b), (n))
607 #define __do_readsw(a, b, n) _insw(PCI_FIX_ADDR(a), (b), (n))
608 #define __do_readsl(a, b, n) _insl(PCI_FIX_ADDR(a), (b), (n))
609 #endif /* !CONFIG_EEH */
610 #define __do_writesb(a, b, n) _outsb(PCI_FIX_ADDR(a),(b),(n))
611 #define __do_writesw(a, b, n) _outsw(PCI_FIX_ADDR(a),(b),(n))
612 #define __do_writesl(a, b, n) _outsl(PCI_FIX_ADDR(a),(b),(n))
614 #define __do_insb(p, b, n) readsb((PCI_IO_ADDR)_IO_BASE+(p), (b), (n))
615 #define __do_insw(p, b, n) readsw((PCI_IO_ADDR)_IO_BASE+(p), (b), (n))
616 #define __do_insl(p, b, n) readsl((PCI_IO_ADDR)_IO_BASE+(p), (b), (n))
617 #define __do_outsb(p, b, n) writesb((PCI_IO_ADDR)_IO_BASE+(p),(b),(n))
618 #define __do_outsw(p, b, n) writesw((PCI_IO_ADDR)_IO_BASE+(p),(b),(n))
619 #define __do_outsl(p, b, n) writesl((PCI_IO_ADDR)_IO_BASE+(p),(b),(n))
621 #define __do_memset_io(addr, c, n) \
622 _memset_io(PCI_FIX_ADDR(addr), c, n)
623 #define __do_memcpy_toio(dst, src, n) \
624 _memcpy_toio(PCI_FIX_ADDR(dst), src, n)
627 #define __do_memcpy_fromio(dst, src, n) \
628 eeh_memcpy_fromio(dst, PCI_FIX_ADDR(src), n)
629 #else /* CONFIG_EEH */
630 #define __do_memcpy_fromio(dst, src, n) \
631 _memcpy_fromio(dst,PCI_FIX_ADDR(src),n)
632 #endif /* !CONFIG_EEH */
634 #ifdef CONFIG_PPC_INDIRECT_PIO
635 #define DEF_PCI_HOOK_pio(x) x
637 #define DEF_PCI_HOOK_pio(x) NULL
640 #ifdef CONFIG_PPC_INDIRECT_MMIO
641 #define DEF_PCI_HOOK_mem(x) x
643 #define DEF_PCI_HOOK_mem(x) NULL
646 /* Structure containing all the hooks */
647 extern struct ppc_pci_io {
649 #define DEF_PCI_AC_RET(name, ret, at, al, space, aa) ret (*name) at;
650 #define DEF_PCI_AC_NORET(name, at, al, space, aa) void (*name) at;
652 #include <asm/io-defs.h>
654 #undef DEF_PCI_AC_RET
655 #undef DEF_PCI_AC_NORET
659 /* The inline wrappers */
660 #define DEF_PCI_AC_RET(name, ret, at, al, space, aa) \
661 static inline ret name at \
663 if (DEF_PCI_HOOK_##space(ppc_pci_io.name) != NULL) \
664 return ppc_pci_io.name al; \
665 return __do_##name al; \
668 #define DEF_PCI_AC_NORET(name, at, al, space, aa) \
669 static inline void name at \
671 if (DEF_PCI_HOOK_##space(ppc_pci_io.name) != NULL) \
672 ppc_pci_io.name al; \
677 #include <asm/io-defs.h>
679 #undef DEF_PCI_AC_RET
680 #undef DEF_PCI_AC_NORET
682 /* Some drivers check for the presence of readq & writeq with
683 * a #ifdef, so we make them happy here.
688 #define writeb writeb
689 #define writew writew
690 #define writel writel
691 #define readsb readsb
692 #define readsw readsw
693 #define readsl readsl
694 #define writesb writesb
695 #define writesw writesw
696 #define writesl writesl
711 #define writeq writeq
713 #define memset_io memset_io
714 #define memcpy_fromio memcpy_fromio
715 #define memcpy_toio memcpy_toio
718 * Convert a physical pointer to a virtual kernel pointer for /dev/mem
721 #define xlate_dev_mem_ptr(p) __va(p)
724 * We don't do relaxed operations yet, at least not with this semantic
726 #define readb_relaxed(addr) readb(addr)
727 #define readw_relaxed(addr) readw(addr)
728 #define readl_relaxed(addr) readl(addr)
729 #define readq_relaxed(addr) readq(addr)
730 #define writeb_relaxed(v, addr) writeb(v, addr)
731 #define writew_relaxed(v, addr) writew(v, addr)
732 #define writel_relaxed(v, addr) writel(v, addr)
733 #define writeq_relaxed(v, addr) writeq(v, addr)
735 #ifdef CONFIG_GENERIC_IOMAP
736 #include <asm-generic/iomap.h>
739 * Here comes the implementation of the IOMAP interfaces.
741 static inline unsigned int ioread16be(const void __iomem *addr)
743 return readw_be(addr);
745 #define ioread16be ioread16be
747 static inline unsigned int ioread32be(const void __iomem *addr)
749 return readl_be(addr);
751 #define ioread32be ioread32be
754 static inline u64 ioread64_lo_hi(const void __iomem *addr)
758 #define ioread64_lo_hi ioread64_lo_hi
760 static inline u64 ioread64_hi_lo(const void __iomem *addr)
764 #define ioread64_hi_lo ioread64_hi_lo
766 static inline u64 ioread64be(const void __iomem *addr)
768 return readq_be(addr);
770 #define ioread64be ioread64be
772 static inline u64 ioread64be_lo_hi(const void __iomem *addr)
774 return readq_be(addr);
776 #define ioread64be_lo_hi ioread64be_lo_hi
778 static inline u64 ioread64be_hi_lo(const void __iomem *addr)
780 return readq_be(addr);
782 #define ioread64be_hi_lo ioread64be_hi_lo
783 #endif /* __powerpc64__ */
785 static inline void iowrite16be(u16 val, void __iomem *addr)
787 writew_be(val, addr);
789 #define iowrite16be iowrite16be
791 static inline void iowrite32be(u32 val, void __iomem *addr)
793 writel_be(val, addr);
795 #define iowrite32be iowrite32be
798 static inline void iowrite64_lo_hi(u64 val, void __iomem *addr)
802 #define iowrite64_lo_hi iowrite64_lo_hi
804 static inline void iowrite64_hi_lo(u64 val, void __iomem *addr)
808 #define iowrite64_hi_lo iowrite64_hi_lo
810 static inline void iowrite64be(u64 val, void __iomem *addr)
812 writeq_be(val, addr);
814 #define iowrite64be iowrite64be
816 static inline void iowrite64be_lo_hi(u64 val, void __iomem *addr)
818 writeq_be(val, addr);
820 #define iowrite64be_lo_hi iowrite64be_lo_hi
822 static inline void iowrite64be_hi_lo(u64 val, void __iomem *addr)
824 writeq_be(val, addr);
826 #define iowrite64be_hi_lo iowrite64be_hi_lo
827 #endif /* __powerpc64__ */
830 void pci_iounmap(struct pci_dev *dev, void __iomem *addr);
831 #define pci_iounmap pci_iounmap
832 void __iomem *ioport_map(unsigned long port, unsigned int len);
833 #define ioport_map ioport_map
836 static inline void iosync(void)
838 __asm__ __volatile__ ("sync" : : : "memory");
841 /* Enforce in-order execution of data I/O.
842 * No distinction between read/write on PPC; use eieio for all three.
843 * Those are fairly week though. They don't provide a barrier between
844 * MMIO and cacheable storage nor do they provide a barrier vs. locks,
845 * they only provide barriers between 2 __raw MMIO operations and
846 * possibly break write combining.
848 #define iobarrier_rw() eieio()
849 #define iobarrier_r() eieio()
850 #define iobarrier_w() eieio()
854 * output pause versions need a delay at least for the
855 * w83c105 ide controller in a p610.
857 #define inb_p(port) inb(port)
858 #define outb_p(val, port) (udelay(1), outb((val), (port)))
859 #define inw_p(port) inw(port)
860 #define outw_p(val, port) (udelay(1), outw((val), (port)))
861 #define inl_p(port) inl(port)
862 #define outl_p(val, port) (udelay(1), outl((val), (port)))
865 #define IO_SPACE_LIMIT ~(0UL)
868 * ioremap - map bus memory into CPU space
869 * @address: bus address of the memory
870 * @size: size of the resource to map
872 * ioremap performs a platform specific sequence of operations to
873 * make bus memory CPU accessible via the readb/readw/readl/writeb/
874 * writew/writel functions and the other mmio helpers. The returned
875 * address is not guaranteed to be usable directly as a virtual
878 * We provide a few variations of it:
880 * * ioremap is the standard one and provides non-cacheable guarded mappings
881 * and can be hooked by the platform via ppc_md
883 * * ioremap_prot allows to specify the page flags as an argument and can
884 * also be hooked by the platform via ppc_md.
886 * * ioremap_wc enables write combining
888 * * ioremap_wt enables write through
890 * * ioremap_coherent maps coherent cached memory
892 * * iounmap undoes such a mapping and can be hooked
894 * * __ioremap_caller is the same as above but takes an explicit caller
895 * reference rather than using __builtin_return_address(0)
898 extern void __iomem *ioremap(phys_addr_t address, unsigned long size);
899 extern void __iomem *ioremap_prot(phys_addr_t address, unsigned long size,
900 unsigned long flags);
901 extern void __iomem *ioremap_wc(phys_addr_t address, unsigned long size);
902 #define ioremap_wc ioremap_wc
905 void __iomem *ioremap_wt(phys_addr_t address, unsigned long size);
906 #define ioremap_wt ioremap_wt
909 void __iomem *ioremap_coherent(phys_addr_t address, unsigned long size);
910 #define ioremap_uc(addr, size) ioremap((addr), (size))
911 #define ioremap_cache(addr, size) \
912 ioremap_prot((addr), (size), pgprot_val(PAGE_KERNEL))
914 extern void iounmap(volatile void __iomem *addr);
916 void __iomem *ioremap_phb(phys_addr_t paddr, unsigned long size);
918 int early_ioremap_range(unsigned long ea, phys_addr_t pa,
919 unsigned long size, pgprot_t prot);
920 void __iomem *do_ioremap(phys_addr_t pa, phys_addr_t offset, unsigned long size,
921 pgprot_t prot, void *caller);
923 extern void __iomem *__ioremap_caller(phys_addr_t, unsigned long size,
924 pgprot_t prot, void *caller);
927 * When CONFIG_PPC_INDIRECT_PIO is set, we use the generic iomap implementation
928 * which needs some additional definitions here. They basically allow PIO
929 * space overall to be 1GB. This will work as long as we never try to use
930 * iomap to map MMIO below 1GB which should be fine on ppc64
932 #define HAVE_ARCH_PIO_SIZE 1
933 #define PIO_OFFSET 0x00000000UL
934 #define PIO_MASK (FULL_IO_SIZE - 1)
935 #define PIO_RESERVED (FULL_IO_SIZE)
937 #define mmio_read16be(addr) readw_be(addr)
938 #define mmio_read32be(addr) readl_be(addr)
939 #define mmio_read64be(addr) readq_be(addr)
940 #define mmio_write16be(val, addr) writew_be(val, addr)
941 #define mmio_write32be(val, addr) writel_be(val, addr)
942 #define mmio_write64be(val, addr) writeq_be(val, addr)
943 #define mmio_insb(addr, dst, count) readsb(addr, dst, count)
944 #define mmio_insw(addr, dst, count) readsw(addr, dst, count)
945 #define mmio_insl(addr, dst, count) readsl(addr, dst, count)
946 #define mmio_outsb(addr, src, count) writesb(addr, src, count)
947 #define mmio_outsw(addr, src, count) writesw(addr, src, count)
948 #define mmio_outsl(addr, src, count) writesl(addr, src, count)
951 * virt_to_phys - map virtual addresses to physical
952 * @address: address to remap
954 * The returned physical address is the physical (CPU) mapping for
955 * the memory address given. It is only valid to use this function on
956 * addresses directly mapped or allocated via kmalloc.
958 * This function does not give bus mappings for DMA transfers. In
959 * almost all conceivable cases a device driver should not be using
962 static inline unsigned long virt_to_phys(volatile void * address)
964 WARN_ON(IS_ENABLED(CONFIG_DEBUG_VIRTUAL) && !virt_addr_valid(address));
966 return __pa((unsigned long)address);
968 #define virt_to_phys virt_to_phys
971 * phys_to_virt - map physical address to virtual
972 * @address: address to remap
974 * The returned virtual address is a current CPU mapping for
975 * the memory address given. It is only valid to use this function on
976 * addresses that have a kernel mapping
978 * This function does not handle bus mappings for DMA transfers. In
979 * almost all conceivable cases a device driver should not be using
982 static inline void * phys_to_virt(unsigned long address)
984 return (void *)__va(address);
986 #define phys_to_virt phys_to_virt
989 * Change "struct page" to physical address.
991 static inline phys_addr_t page_to_phys(struct page *page)
993 unsigned long pfn = page_to_pfn(page);
995 WARN_ON(IS_ENABLED(CONFIG_DEBUG_VIRTUAL) && !pfn_valid(pfn));
997 return PFN_PHYS(pfn);
1001 * 32 bits still uses virt_to_bus() for it's implementation of DMA
1002 * mappings se we have to keep it defined here. We also have some old
1003 * drivers (shame shame shame) that use bus_to_virt() and haven't been
1004 * fixed yet so I need to define it here.
1008 static inline unsigned long virt_to_bus(volatile void * address)
1010 if (address == NULL)
1012 return __pa(address) + PCI_DRAM_OFFSET;
1014 #define virt_to_bus virt_to_bus
1016 static inline void * bus_to_virt(unsigned long address)
1020 return __va(address - PCI_DRAM_OFFSET);
1022 #define bus_to_virt bus_to_virt
1024 #endif /* CONFIG_PPC32 */
1027 #define setbits32(_addr, _v) out_be32((_addr), in_be32(_addr) | (_v))
1028 #define clrbits32(_addr, _v) out_be32((_addr), in_be32(_addr) & ~(_v))
1030 #define setbits16(_addr, _v) out_be16((_addr), in_be16(_addr) | (_v))
1031 #define clrbits16(_addr, _v) out_be16((_addr), in_be16(_addr) & ~(_v))
1033 #define setbits8(_addr, _v) out_8((_addr), in_8(_addr) | (_v))
1034 #define clrbits8(_addr, _v) out_8((_addr), in_8(_addr) & ~(_v))
1036 /* Clear and set bits in one shot. These macros can be used to clear and
1037 * set multiple bits in a register using a single read-modify-write. These
1038 * macros can also be used to set a multiple-bit bit pattern using a mask,
1039 * by specifying the mask in the 'clear' parameter and the new bit pattern
1040 * in the 'set' parameter.
1043 #define clrsetbits(type, addr, clear, set) \
1044 out_##type((addr), (in_##type(addr) & ~(clear)) | (set))
1046 #ifdef __powerpc64__
1047 #define clrsetbits_be64(addr, clear, set) clrsetbits(be64, addr, clear, set)
1048 #define clrsetbits_le64(addr, clear, set) clrsetbits(le64, addr, clear, set)
1051 #define clrsetbits_be32(addr, clear, set) clrsetbits(be32, addr, clear, set)
1052 #define clrsetbits_le32(addr, clear, set) clrsetbits(le32, addr, clear, set)
1054 #define clrsetbits_be16(addr, clear, set) clrsetbits(be16, addr, clear, set)
1055 #define clrsetbits_le16(addr, clear, set) clrsetbits(le16, addr, clear, set)
1057 #define clrsetbits_8(addr, clear, set) clrsetbits(8, addr, clear, set)
1059 #include <asm-generic/io.h>
1061 #endif /* __KERNEL__ */
1063 #endif /* _ASM_POWERPC_IO_H */