2 * Contains CPU feature definitions
4 * Copyright (C) 2015 ARM Ltd.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program. If not, see <http://www.gnu.org/licenses/>.
19 #define pr_fmt(fmt) "CPU features: " fmt
21 #include <linux/bsearch.h>
22 #include <linux/cpumask.h>
23 #include <linux/percpu.h>
24 #include <linux/sort.h>
25 #include <linux/stop_machine.h>
26 #include <linux/types.h>
28 #include <linux/cpu.h>
31 #include <asm/cpufeature.h>
32 #include <asm/cpu_ops.h>
33 #include <asm/mmu_context.h>
34 #include <asm/processor.h>
35 #include <asm/sysreg.h>
36 #include <asm/traps.h>
37 #include <asm/vectors.h>
40 unsigned long elf_hwcap __read_mostly;
41 EXPORT_SYMBOL_GPL(elf_hwcap);
44 #define COMPAT_ELF_HWCAP_DEFAULT \
45 (COMPAT_HWCAP_HALF|COMPAT_HWCAP_THUMB|\
46 COMPAT_HWCAP_FAST_MULT|COMPAT_HWCAP_EDSP|\
47 COMPAT_HWCAP_TLS|COMPAT_HWCAP_IDIV|\
49 unsigned int compat_elf_hwcap __read_mostly = COMPAT_ELF_HWCAP_DEFAULT;
50 unsigned int compat_elf_hwcap2 __read_mostly;
53 DECLARE_BITMAP(cpu_hwcaps, ARM64_NCAPS);
54 EXPORT_SYMBOL(cpu_hwcaps);
56 DEFINE_PER_CPU_READ_MOSTLY(const char *, this_cpu_vector) = vectors;
58 static int dump_cpu_hwcaps(struct notifier_block *self, unsigned long v, void *p)
60 /* file-wide pr_fmt adds "CPU features: " prefix */
61 pr_emerg("0x%*pb\n", ARM64_NCAPS, &cpu_hwcaps);
65 static struct notifier_block cpu_hwcaps_notifier = {
66 .notifier_call = dump_cpu_hwcaps
69 static int __init register_cpu_hwcaps_dumper(void)
71 atomic_notifier_chain_register(&panic_notifier_list,
72 &cpu_hwcaps_notifier);
75 __initcall(register_cpu_hwcaps_dumper);
77 DEFINE_STATIC_KEY_ARRAY_FALSE(cpu_hwcap_keys, ARM64_NCAPS);
78 EXPORT_SYMBOL(cpu_hwcap_keys);
80 #define __ARM64_FTR_BITS(SIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \
88 .safe_val = SAFE_VAL, \
91 /* Define a feature with unsigned values */
92 #define ARM64_FTR_BITS(VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \
93 __ARM64_FTR_BITS(FTR_UNSIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL)
95 /* Define a feature with a signed value */
96 #define S_ARM64_FTR_BITS(VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \
97 __ARM64_FTR_BITS(FTR_SIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL)
99 #define ARM64_FTR_END \
104 /* meta feature for alternatives */
105 static bool __maybe_unused
106 cpufeature_pan_not_uao(const struct arm64_cpu_capabilities *entry, int __unused);
110 * NOTE: Any changes to the visibility of features should be kept in
111 * sync with the documentation of the CPU feature register ABI.
113 static const struct arm64_ftr_bits ftr_id_aa64isar0[] = {
114 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_TS_SHIFT, 4, 0),
115 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_FHM_SHIFT, 4, 0),
116 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_DP_SHIFT, 4, 0),
117 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SM4_SHIFT, 4, 0),
118 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SM3_SHIFT, 4, 0),
119 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA3_SHIFT, 4, 0),
120 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_RDM_SHIFT, 4, 0),
121 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_ATOMICS_SHIFT, 4, 0),
122 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_CRC32_SHIFT, 4, 0),
123 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA2_SHIFT, 4, 0),
124 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA1_SHIFT, 4, 0),
125 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_AES_SHIFT, 4, 0),
129 static const struct arm64_ftr_bits ftr_id_aa64isar1[] = {
130 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_LRCPC_SHIFT, 4, 0),
131 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_FCMA_SHIFT, 4, 0),
132 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_JSCVT_SHIFT, 4, 0),
133 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_DPB_SHIFT, 4, 0),
137 static const struct arm64_ftr_bits ftr_id_aa64isar2[] = {
138 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_HIGHER_SAFE, ID_AA64ISAR2_CLEARBHB_SHIFT, 4, 0),
142 static const struct arm64_ftr_bits ftr_id_aa64pfr0[] = {
143 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_CSV3_SHIFT, 4, 0),
144 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_CSV2_SHIFT, 4, 0),
145 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_DIT_SHIFT, 4, 0),
146 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_GIC_SHIFT, 4, 0),
147 S_ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_ASIMD_SHIFT, 4, ID_AA64PFR0_ASIMD_NI),
148 S_ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_FP_SHIFT, 4, ID_AA64PFR0_FP_NI),
149 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL3_SHIFT, 4, 0),
150 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL2_SHIFT, 4, 0),
151 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_SHIFT, 4, ID_AA64PFR0_EL1_64BIT_ONLY),
152 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL0_SHIFT, 4, ID_AA64PFR0_EL0_64BIT_ONLY),
156 static const struct arm64_ftr_bits ftr_id_aa64pfr1[] = {
157 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_SSBS_SHIFT, 4, ID_AA64PFR1_SSBS_PSTATE_NI),
161 static const struct arm64_ftr_bits ftr_id_aa64mmfr0[] = {
162 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_TGRAN4_SHIFT, 4, ID_AA64MMFR0_TGRAN4_NI),
163 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_TGRAN64_SHIFT, 4, ID_AA64MMFR0_TGRAN64_NI),
164 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_TGRAN16_SHIFT, 4, ID_AA64MMFR0_TGRAN16_NI),
165 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_BIGENDEL0_SHIFT, 4, 0),
166 /* Linux shouldn't care about secure memory */
167 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_SNSMEM_SHIFT, 4, 0),
168 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_BIGENDEL_SHIFT, 4, 0),
169 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_ASID_SHIFT, 4, 0),
171 * Differing PARange is fine as long as all peripherals and memory are mapped
172 * within the minimum PARange of all CPUs
174 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_PARANGE_SHIFT, 4, 0),
178 static const struct arm64_ftr_bits ftr_id_aa64mmfr1[] = {
179 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_PAN_SHIFT, 4, 0),
180 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_LOR_SHIFT, 4, 0),
181 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_HPD_SHIFT, 4, 0),
182 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_VHE_SHIFT, 4, 0),
183 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_VMIDBITS_SHIFT, 4, 0),
184 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_HADBS_SHIFT, 4, 0),
188 static const struct arm64_ftr_bits ftr_id_aa64mmfr2[] = {
189 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_AT_SHIFT, 4, 0),
190 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_LVA_SHIFT, 4, 0),
191 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_IESB_SHIFT, 4, 0),
192 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_LSM_SHIFT, 4, 0),
193 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_UAO_SHIFT, 4, 0),
194 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_CNP_SHIFT, 4, 0),
198 static const struct arm64_ftr_bits ftr_ctr[] = {
199 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, 31, 1, 1), /* RES1 */
200 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, 29, 1, 1), /* DIC */
201 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, 28, 1, 1), /* IDC */
202 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_HIGHER_OR_ZERO_SAFE, 24, 4, 0), /* CWG */
203 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_HIGHER_OR_ZERO_SAFE, 20, 4, 0), /* ERG */
204 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_DMINLINE_SHIFT, 4, 1),
206 * Linux can handle differing I-cache policies. Userspace JITs will
207 * make use of *minLine.
208 * If we have differing I-cache policies, report it as the weakest - VIPT.
210 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_EXACT, 14, 2, ICACHE_POLICY_VIPT), /* L1Ip */
211 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_IMINLINE_SHIFT, 4, 0),
215 struct arm64_ftr_reg arm64_ftr_reg_ctrel0 = {
216 .name = "SYS_CTR_EL0",
220 static const struct arm64_ftr_bits ftr_id_mmfr0[] = {
221 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 28, 4, 0xf), /* InnerShr */
222 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 24, 4, 0), /* FCSE */
223 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, 20, 4, 0), /* AuxReg */
224 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 0), /* TCM */
225 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0), /* ShareLvl */
226 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0xf), /* OuterShr */
227 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0), /* PMSA */
228 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0), /* VMSA */
232 static const struct arm64_ftr_bits ftr_id_aa64dfr0[] = {
233 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, 36, 28, 0),
234 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64DFR0_PMSVER_SHIFT, 4, 0),
235 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_CTX_CMPS_SHIFT, 4, 0),
236 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_WRPS_SHIFT, 4, 0),
237 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_BRPS_SHIFT, 4, 0),
239 * We can instantiate multiple PMU instances with different levels
242 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64DFR0_PMUVER_SHIFT, 4, 0),
243 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64DFR0_DEBUGVER_SHIFT, 4, 0x6),
247 static const struct arm64_ftr_bits ftr_mvfr2[] = {
248 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0), /* FPMisc */
249 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0), /* SIMDMisc */
253 static const struct arm64_ftr_bits ftr_dczid[] = {
254 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, 4, 1, 1), /* DZP */
255 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0), /* BS */
260 static const struct arm64_ftr_bits ftr_id_isar5[] = {
261 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_RDM_SHIFT, 4, 0),
262 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_CRC32_SHIFT, 4, 0),
263 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_SHA2_SHIFT, 4, 0),
264 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_SHA1_SHIFT, 4, 0),
265 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_AES_SHIFT, 4, 0),
266 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_SEVL_SHIFT, 4, 0),
270 static const struct arm64_ftr_bits ftr_id_mmfr4[] = {
271 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0), /* ac2 */
275 static const struct arm64_ftr_bits ftr_id_pfr0[] = {
276 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0), /* State3 */
277 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0), /* State2 */
278 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0), /* State1 */
279 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0), /* State0 */
283 static const struct arm64_ftr_bits ftr_id_dfr0[] = {
284 /* [31:28] TraceFilt */
285 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 24, 4, 0xf), /* PerfMon */
286 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 20, 4, 0),
287 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 0),
288 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0),
289 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0),
290 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0),
291 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0),
296 * Common ftr bits for a 32bit register with all hidden, strict
297 * attributes, with 4bit feature fields and a default safe value of
298 * 0. Covers the following 32bit registers:
299 * id_isar[0-4], id_mmfr[1-3], id_pfr1, mvfr[0-1]
301 static const struct arm64_ftr_bits ftr_generic_32bits[] = {
302 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 28, 4, 0),
303 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 24, 4, 0),
304 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 20, 4, 0),
305 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 0),
306 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0),
307 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0),
308 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0),
309 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0),
313 /* Table for a single 32bit feature value */
314 static const struct arm64_ftr_bits ftr_single32[] = {
315 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, 0, 32, 0),
319 static const struct arm64_ftr_bits ftr_raz[] = {
323 #define ARM64_FTR_REG(id, table) { \
325 .reg = &(struct arm64_ftr_reg){ \
327 .ftr_bits = &((table)[0]), \
330 static const struct __ftr_reg_entry {
332 struct arm64_ftr_reg *reg;
333 } arm64_ftr_regs[] = {
335 /* Op1 = 0, CRn = 0, CRm = 1 */
336 ARM64_FTR_REG(SYS_ID_PFR0_EL1, ftr_id_pfr0),
337 ARM64_FTR_REG(SYS_ID_PFR1_EL1, ftr_generic_32bits),
338 ARM64_FTR_REG(SYS_ID_DFR0_EL1, ftr_id_dfr0),
339 ARM64_FTR_REG(SYS_ID_MMFR0_EL1, ftr_id_mmfr0),
340 ARM64_FTR_REG(SYS_ID_MMFR1_EL1, ftr_generic_32bits),
341 ARM64_FTR_REG(SYS_ID_MMFR2_EL1, ftr_generic_32bits),
342 ARM64_FTR_REG(SYS_ID_MMFR3_EL1, ftr_generic_32bits),
344 /* Op1 = 0, CRn = 0, CRm = 2 */
345 ARM64_FTR_REG(SYS_ID_ISAR0_EL1, ftr_generic_32bits),
346 ARM64_FTR_REG(SYS_ID_ISAR1_EL1, ftr_generic_32bits),
347 ARM64_FTR_REG(SYS_ID_ISAR2_EL1, ftr_generic_32bits),
348 ARM64_FTR_REG(SYS_ID_ISAR3_EL1, ftr_generic_32bits),
349 ARM64_FTR_REG(SYS_ID_ISAR4_EL1, ftr_generic_32bits),
350 ARM64_FTR_REG(SYS_ID_ISAR5_EL1, ftr_id_isar5),
351 ARM64_FTR_REG(SYS_ID_MMFR4_EL1, ftr_id_mmfr4),
353 /* Op1 = 0, CRn = 0, CRm = 3 */
354 ARM64_FTR_REG(SYS_MVFR0_EL1, ftr_generic_32bits),
355 ARM64_FTR_REG(SYS_MVFR1_EL1, ftr_generic_32bits),
356 ARM64_FTR_REG(SYS_MVFR2_EL1, ftr_mvfr2),
358 /* Op1 = 0, CRn = 0, CRm = 4 */
359 ARM64_FTR_REG(SYS_ID_AA64PFR0_EL1, ftr_id_aa64pfr0),
360 ARM64_FTR_REG(SYS_ID_AA64PFR1_EL1, ftr_id_aa64pfr1),
362 /* Op1 = 0, CRn = 0, CRm = 5 */
363 ARM64_FTR_REG(SYS_ID_AA64DFR0_EL1, ftr_id_aa64dfr0),
364 ARM64_FTR_REG(SYS_ID_AA64DFR1_EL1, ftr_raz),
366 /* Op1 = 0, CRn = 0, CRm = 6 */
367 ARM64_FTR_REG(SYS_ID_AA64ISAR0_EL1, ftr_id_aa64isar0),
368 ARM64_FTR_REG(SYS_ID_AA64ISAR1_EL1, ftr_id_aa64isar1),
369 ARM64_FTR_REG(SYS_ID_AA64ISAR2_EL1, ftr_id_aa64isar2),
371 /* Op1 = 0, CRn = 0, CRm = 7 */
372 ARM64_FTR_REG(SYS_ID_AA64MMFR0_EL1, ftr_id_aa64mmfr0),
373 ARM64_FTR_REG(SYS_ID_AA64MMFR1_EL1, ftr_id_aa64mmfr1),
374 ARM64_FTR_REG(SYS_ID_AA64MMFR2_EL1, ftr_id_aa64mmfr2),
376 /* Op1 = 3, CRn = 0, CRm = 0 */
377 { SYS_CTR_EL0, &arm64_ftr_reg_ctrel0 },
378 ARM64_FTR_REG(SYS_DCZID_EL0, ftr_dczid),
380 /* Op1 = 3, CRn = 14, CRm = 0 */
381 ARM64_FTR_REG(SYS_CNTFRQ_EL0, ftr_single32),
384 static int search_cmp_ftr_reg(const void *id, const void *regp)
386 return (int)(unsigned long)id - (int)((const struct __ftr_reg_entry *)regp)->sys_id;
390 * get_arm64_ftr_reg - Lookup a feature register entry using its
391 * sys_reg() encoding. With the array arm64_ftr_regs sorted in the
392 * ascending order of sys_id , we use binary search to find a matching
395 * returns - Upon success, matching ftr_reg entry for id.
396 * - NULL on failure. It is upto the caller to decide
397 * the impact of a failure.
399 static struct arm64_ftr_reg *get_arm64_ftr_reg(u32 sys_id)
401 const struct __ftr_reg_entry *ret;
403 ret = bsearch((const void *)(unsigned long)sys_id,
405 ARRAY_SIZE(arm64_ftr_regs),
406 sizeof(arm64_ftr_regs[0]),
413 static u64 arm64_ftr_set_value(const struct arm64_ftr_bits *ftrp, s64 reg,
416 u64 mask = arm64_ftr_mask(ftrp);
419 reg |= (ftr_val << ftrp->shift) & mask;
423 static s64 arm64_ftr_safe_value(const struct arm64_ftr_bits *ftrp, s64 new,
428 switch (ftrp->type) {
430 ret = ftrp->safe_val;
433 ret = new < cur ? new : cur;
435 case FTR_HIGHER_OR_ZERO_SAFE:
439 case FTR_HIGHER_SAFE:
440 ret = new > cur ? new : cur;
449 static void __init sort_ftr_regs(void)
453 /* Check that the array is sorted so that we can do the binary search */
454 for (i = 1; i < ARRAY_SIZE(arm64_ftr_regs); i++)
455 BUG_ON(arm64_ftr_regs[i].sys_id < arm64_ftr_regs[i - 1].sys_id);
459 * Initialise the CPU feature register from Boot CPU values.
460 * Also initiliases the strict_mask for the register.
461 * Any bits that are not covered by an arm64_ftr_bits entry are considered
462 * RES0 for the system-wide value, and must strictly match.
464 static void __init init_cpu_ftr_reg(u32 sys_reg, u64 new)
467 u64 strict_mask = ~0x0ULL;
471 const struct arm64_ftr_bits *ftrp;
472 struct arm64_ftr_reg *reg = get_arm64_ftr_reg(sys_reg);
476 for (ftrp = reg->ftr_bits; ftrp->width; ftrp++) {
477 u64 ftr_mask = arm64_ftr_mask(ftrp);
478 s64 ftr_new = arm64_ftr_value(ftrp, new);
480 val = arm64_ftr_set_value(ftrp, val, ftr_new);
482 valid_mask |= ftr_mask;
484 strict_mask &= ~ftr_mask;
486 user_mask |= ftr_mask;
488 reg->user_val = arm64_ftr_set_value(ftrp,
496 reg->strict_mask = strict_mask;
497 reg->user_mask = user_mask;
500 extern const struct arm64_cpu_capabilities arm64_errata[];
501 static void __init setup_boot_cpu_capabilities(void);
503 void __init init_cpu_features(struct cpuinfo_arm64 *info)
505 /* Before we start using the tables, make sure it is sorted */
508 init_cpu_ftr_reg(SYS_CTR_EL0, info->reg_ctr);
509 init_cpu_ftr_reg(SYS_DCZID_EL0, info->reg_dczid);
510 init_cpu_ftr_reg(SYS_CNTFRQ_EL0, info->reg_cntfrq);
511 init_cpu_ftr_reg(SYS_ID_AA64DFR0_EL1, info->reg_id_aa64dfr0);
512 init_cpu_ftr_reg(SYS_ID_AA64DFR1_EL1, info->reg_id_aa64dfr1);
513 init_cpu_ftr_reg(SYS_ID_AA64ISAR0_EL1, info->reg_id_aa64isar0);
514 init_cpu_ftr_reg(SYS_ID_AA64ISAR1_EL1, info->reg_id_aa64isar1);
515 init_cpu_ftr_reg(SYS_ID_AA64ISAR2_EL1, info->reg_id_aa64isar2);
516 init_cpu_ftr_reg(SYS_ID_AA64MMFR0_EL1, info->reg_id_aa64mmfr0);
517 init_cpu_ftr_reg(SYS_ID_AA64MMFR1_EL1, info->reg_id_aa64mmfr1);
518 init_cpu_ftr_reg(SYS_ID_AA64MMFR2_EL1, info->reg_id_aa64mmfr2);
519 init_cpu_ftr_reg(SYS_ID_AA64PFR0_EL1, info->reg_id_aa64pfr0);
520 init_cpu_ftr_reg(SYS_ID_AA64PFR1_EL1, info->reg_id_aa64pfr1);
522 if (id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) {
523 init_cpu_ftr_reg(SYS_ID_DFR0_EL1, info->reg_id_dfr0);
524 init_cpu_ftr_reg(SYS_ID_ISAR0_EL1, info->reg_id_isar0);
525 init_cpu_ftr_reg(SYS_ID_ISAR1_EL1, info->reg_id_isar1);
526 init_cpu_ftr_reg(SYS_ID_ISAR2_EL1, info->reg_id_isar2);
527 init_cpu_ftr_reg(SYS_ID_ISAR3_EL1, info->reg_id_isar3);
528 init_cpu_ftr_reg(SYS_ID_ISAR4_EL1, info->reg_id_isar4);
529 init_cpu_ftr_reg(SYS_ID_ISAR5_EL1, info->reg_id_isar5);
530 init_cpu_ftr_reg(SYS_ID_MMFR0_EL1, info->reg_id_mmfr0);
531 init_cpu_ftr_reg(SYS_ID_MMFR1_EL1, info->reg_id_mmfr1);
532 init_cpu_ftr_reg(SYS_ID_MMFR2_EL1, info->reg_id_mmfr2);
533 init_cpu_ftr_reg(SYS_ID_MMFR3_EL1, info->reg_id_mmfr3);
534 init_cpu_ftr_reg(SYS_ID_PFR0_EL1, info->reg_id_pfr0);
535 init_cpu_ftr_reg(SYS_ID_PFR1_EL1, info->reg_id_pfr1);
536 init_cpu_ftr_reg(SYS_MVFR0_EL1, info->reg_mvfr0);
537 init_cpu_ftr_reg(SYS_MVFR1_EL1, info->reg_mvfr1);
538 init_cpu_ftr_reg(SYS_MVFR2_EL1, info->reg_mvfr2);
542 * Detect and enable early CPU capabilities based on the boot CPU,
543 * after we have initialised the CPU feature infrastructure.
545 setup_boot_cpu_capabilities();
548 static void update_cpu_ftr_reg(struct arm64_ftr_reg *reg, u64 new)
550 const struct arm64_ftr_bits *ftrp;
552 for (ftrp = reg->ftr_bits; ftrp->width; ftrp++) {
553 s64 ftr_cur = arm64_ftr_value(ftrp, reg->sys_val);
554 s64 ftr_new = arm64_ftr_value(ftrp, new);
556 if (ftr_cur == ftr_new)
558 /* Find a safe value */
559 ftr_new = arm64_ftr_safe_value(ftrp, ftr_new, ftr_cur);
560 reg->sys_val = arm64_ftr_set_value(ftrp, reg->sys_val, ftr_new);
565 static int check_update_ftr_reg(u32 sys_id, int cpu, u64 val, u64 boot)
567 struct arm64_ftr_reg *regp = get_arm64_ftr_reg(sys_id);
570 update_cpu_ftr_reg(regp, val);
571 if ((boot & regp->strict_mask) == (val & regp->strict_mask))
573 pr_warn("SANITY CHECK: Unexpected variation in %s. Boot CPU: %#016llx, CPU%d: %#016llx\n",
574 regp->name, boot, cpu, val);
579 * Update system wide CPU feature registers with the values from a
580 * non-boot CPU. Also performs SANITY checks to make sure that there
581 * aren't any insane variations from that of the boot CPU.
583 void update_cpu_features(int cpu,
584 struct cpuinfo_arm64 *info,
585 struct cpuinfo_arm64 *boot)
590 * The kernel can handle differing I-cache policies, but otherwise
591 * caches should look identical. Userspace JITs will make use of
594 taint |= check_update_ftr_reg(SYS_CTR_EL0, cpu,
595 info->reg_ctr, boot->reg_ctr);
598 * Userspace may perform DC ZVA instructions. Mismatched block sizes
599 * could result in too much or too little memory being zeroed if a
600 * process is preempted and migrated between CPUs.
602 taint |= check_update_ftr_reg(SYS_DCZID_EL0, cpu,
603 info->reg_dczid, boot->reg_dczid);
605 /* If different, timekeeping will be broken (especially with KVM) */
606 taint |= check_update_ftr_reg(SYS_CNTFRQ_EL0, cpu,
607 info->reg_cntfrq, boot->reg_cntfrq);
610 * The kernel uses self-hosted debug features and expects CPUs to
611 * support identical debug features. We presently need CTX_CMPs, WRPs,
612 * and BRPs to be identical.
613 * ID_AA64DFR1 is currently RES0.
615 taint |= check_update_ftr_reg(SYS_ID_AA64DFR0_EL1, cpu,
616 info->reg_id_aa64dfr0, boot->reg_id_aa64dfr0);
617 taint |= check_update_ftr_reg(SYS_ID_AA64DFR1_EL1, cpu,
618 info->reg_id_aa64dfr1, boot->reg_id_aa64dfr1);
620 * Even in big.LITTLE, processors should be identical instruction-set
623 taint |= check_update_ftr_reg(SYS_ID_AA64ISAR0_EL1, cpu,
624 info->reg_id_aa64isar0, boot->reg_id_aa64isar0);
625 taint |= check_update_ftr_reg(SYS_ID_AA64ISAR1_EL1, cpu,
626 info->reg_id_aa64isar1, boot->reg_id_aa64isar1);
627 taint |= check_update_ftr_reg(SYS_ID_AA64ISAR2_EL1, cpu,
628 info->reg_id_aa64isar2, boot->reg_id_aa64isar2);
631 * Differing PARange support is fine as long as all peripherals and
632 * memory are mapped within the minimum PARange of all CPUs.
633 * Linux should not care about secure memory.
635 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR0_EL1, cpu,
636 info->reg_id_aa64mmfr0, boot->reg_id_aa64mmfr0);
637 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR1_EL1, cpu,
638 info->reg_id_aa64mmfr1, boot->reg_id_aa64mmfr1);
639 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR2_EL1, cpu,
640 info->reg_id_aa64mmfr2, boot->reg_id_aa64mmfr2);
642 taint |= check_update_ftr_reg(SYS_ID_AA64PFR0_EL1, cpu,
643 info->reg_id_aa64pfr0, boot->reg_id_aa64pfr0);
644 taint |= check_update_ftr_reg(SYS_ID_AA64PFR1_EL1, cpu,
645 info->reg_id_aa64pfr1, boot->reg_id_aa64pfr1);
648 * If we have AArch32, we care about 32-bit features for compat.
649 * If the system doesn't support AArch32, don't update them.
651 if (id_aa64pfr0_32bit_el0(read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1)) &&
652 id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) {
654 taint |= check_update_ftr_reg(SYS_ID_DFR0_EL1, cpu,
655 info->reg_id_dfr0, boot->reg_id_dfr0);
656 taint |= check_update_ftr_reg(SYS_ID_ISAR0_EL1, cpu,
657 info->reg_id_isar0, boot->reg_id_isar0);
658 taint |= check_update_ftr_reg(SYS_ID_ISAR1_EL1, cpu,
659 info->reg_id_isar1, boot->reg_id_isar1);
660 taint |= check_update_ftr_reg(SYS_ID_ISAR2_EL1, cpu,
661 info->reg_id_isar2, boot->reg_id_isar2);
662 taint |= check_update_ftr_reg(SYS_ID_ISAR3_EL1, cpu,
663 info->reg_id_isar3, boot->reg_id_isar3);
664 taint |= check_update_ftr_reg(SYS_ID_ISAR4_EL1, cpu,
665 info->reg_id_isar4, boot->reg_id_isar4);
666 taint |= check_update_ftr_reg(SYS_ID_ISAR5_EL1, cpu,
667 info->reg_id_isar5, boot->reg_id_isar5);
670 * Regardless of the value of the AuxReg field, the AIFSR, ADFSR, and
671 * ACTLR formats could differ across CPUs and therefore would have to
672 * be trapped for virtualization anyway.
674 taint |= check_update_ftr_reg(SYS_ID_MMFR0_EL1, cpu,
675 info->reg_id_mmfr0, boot->reg_id_mmfr0);
676 taint |= check_update_ftr_reg(SYS_ID_MMFR1_EL1, cpu,
677 info->reg_id_mmfr1, boot->reg_id_mmfr1);
678 taint |= check_update_ftr_reg(SYS_ID_MMFR2_EL1, cpu,
679 info->reg_id_mmfr2, boot->reg_id_mmfr2);
680 taint |= check_update_ftr_reg(SYS_ID_MMFR3_EL1, cpu,
681 info->reg_id_mmfr3, boot->reg_id_mmfr3);
682 taint |= check_update_ftr_reg(SYS_ID_PFR0_EL1, cpu,
683 info->reg_id_pfr0, boot->reg_id_pfr0);
684 taint |= check_update_ftr_reg(SYS_ID_PFR1_EL1, cpu,
685 info->reg_id_pfr1, boot->reg_id_pfr1);
686 taint |= check_update_ftr_reg(SYS_MVFR0_EL1, cpu,
687 info->reg_mvfr0, boot->reg_mvfr0);
688 taint |= check_update_ftr_reg(SYS_MVFR1_EL1, cpu,
689 info->reg_mvfr1, boot->reg_mvfr1);
690 taint |= check_update_ftr_reg(SYS_MVFR2_EL1, cpu,
691 info->reg_mvfr2, boot->reg_mvfr2);
695 * Mismatched CPU features are a recipe for disaster. Don't even
696 * pretend to support them.
699 pr_warn_once("Unsupported CPU feature variation detected.\n");
700 add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_STILL_OK);
704 u64 read_sanitised_ftr_reg(u32 id)
706 struct arm64_ftr_reg *regp = get_arm64_ftr_reg(id);
708 /* We shouldn't get a request for an unsupported register */
710 return regp->sys_val;
713 #define read_sysreg_case(r) \
714 case r: return read_sysreg_s(r)
717 * __read_sysreg_by_encoding() - Used by a STARTING cpu before cpuinfo is populated.
718 * Read the system register on the current CPU
720 static u64 __read_sysreg_by_encoding(u32 sys_id)
723 read_sysreg_case(SYS_ID_PFR0_EL1);
724 read_sysreg_case(SYS_ID_PFR1_EL1);
725 read_sysreg_case(SYS_ID_DFR0_EL1);
726 read_sysreg_case(SYS_ID_MMFR0_EL1);
727 read_sysreg_case(SYS_ID_MMFR1_EL1);
728 read_sysreg_case(SYS_ID_MMFR2_EL1);
729 read_sysreg_case(SYS_ID_MMFR3_EL1);
730 read_sysreg_case(SYS_ID_ISAR0_EL1);
731 read_sysreg_case(SYS_ID_ISAR1_EL1);
732 read_sysreg_case(SYS_ID_ISAR2_EL1);
733 read_sysreg_case(SYS_ID_ISAR3_EL1);
734 read_sysreg_case(SYS_ID_ISAR4_EL1);
735 read_sysreg_case(SYS_ID_ISAR5_EL1);
736 read_sysreg_case(SYS_MVFR0_EL1);
737 read_sysreg_case(SYS_MVFR1_EL1);
738 read_sysreg_case(SYS_MVFR2_EL1);
740 read_sysreg_case(SYS_ID_AA64PFR0_EL1);
741 read_sysreg_case(SYS_ID_AA64PFR1_EL1);
742 read_sysreg_case(SYS_ID_AA64DFR0_EL1);
743 read_sysreg_case(SYS_ID_AA64DFR1_EL1);
744 read_sysreg_case(SYS_ID_AA64MMFR0_EL1);
745 read_sysreg_case(SYS_ID_AA64MMFR1_EL1);
746 read_sysreg_case(SYS_ID_AA64MMFR2_EL1);
747 read_sysreg_case(SYS_ID_AA64ISAR0_EL1);
748 read_sysreg_case(SYS_ID_AA64ISAR1_EL1);
749 read_sysreg_case(SYS_ID_AA64ISAR2_EL1);
751 read_sysreg_case(SYS_CNTFRQ_EL0);
752 read_sysreg_case(SYS_CTR_EL0);
753 read_sysreg_case(SYS_DCZID_EL0);
761 #include <linux/irqchip/arm-gic-v3.h>
764 feature_matches(u64 reg, const struct arm64_cpu_capabilities *entry)
766 int val = cpuid_feature_extract_field(reg, entry->field_pos, entry->sign);
768 return val >= entry->min_field_value;
772 has_cpuid_feature(const struct arm64_cpu_capabilities *entry, int scope)
776 WARN_ON(scope == SCOPE_LOCAL_CPU && preemptible());
777 if (scope == SCOPE_SYSTEM)
778 val = read_sanitised_ftr_reg(entry->sys_reg);
780 val = __read_sysreg_by_encoding(entry->sys_reg);
782 return feature_matches(val, entry);
785 static bool has_useable_gicv3_cpuif(const struct arm64_cpu_capabilities *entry, int scope)
789 if (!has_cpuid_feature(entry, scope))
792 has_sre = gic_enable_sre();
794 pr_warn_once("%s present but disabled by higher exception level\n",
800 static bool has_no_hw_prefetch(const struct arm64_cpu_capabilities *entry, int __unused)
802 u32 midr = read_cpuid_id();
804 /* Cavium ThunderX pass 1.x and 2.x */
805 return MIDR_IS_CPU_MODEL_RANGE(midr, MIDR_THUNDERX,
806 MIDR_CPU_VAR_REV(0, 0),
807 MIDR_CPU_VAR_REV(1, MIDR_REVISION_MASK));
810 static bool hyp_offset_low(const struct arm64_cpu_capabilities *entry,
813 phys_addr_t idmap_addr = __pa_symbol(__hyp_idmap_text_start);
816 * Activate the lower HYP offset only if:
817 * - the idmap doesn't clash with it,
818 * - the kernel is not running at EL2.
820 return idmap_addr > GENMASK(VA_BITS - 2, 0) && !is_kernel_in_hyp_mode();
823 static bool has_no_fpsimd(const struct arm64_cpu_capabilities *entry, int __unused)
825 u64 pfr0 = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1);
827 return cpuid_feature_extract_signed_field(pfr0,
828 ID_AA64PFR0_FP_SHIFT) < 0;
831 static bool __meltdown_safe = true;
832 static int __kpti_forced; /* 0: not forced, >0: forced on, <0: forced off */
834 static bool unmap_kernel_at_el0(const struct arm64_cpu_capabilities *entry,
837 /* List of CPUs that are not vulnerable and don't need KPTI */
838 static const struct midr_range kpti_safe_list[] = {
839 MIDR_ALL_VERSIONS(MIDR_CAVIUM_THUNDERX2),
840 MIDR_ALL_VERSIONS(MIDR_BRCM_VULCAN),
841 MIDR_ALL_VERSIONS(MIDR_CORTEX_A35),
842 MIDR_ALL_VERSIONS(MIDR_CORTEX_A53),
843 MIDR_ALL_VERSIONS(MIDR_CORTEX_A55),
844 MIDR_ALL_VERSIONS(MIDR_CORTEX_A57),
845 MIDR_ALL_VERSIONS(MIDR_CORTEX_A72),
846 MIDR_ALL_VERSIONS(MIDR_CORTEX_A73),
849 char const *str = "kpti command line option";
852 meltdown_safe = is_midr_in_range_list(read_cpuid_id(), kpti_safe_list);
854 /* Defer to CPU feature registers */
855 if (has_cpuid_feature(entry, scope))
856 meltdown_safe = true;
859 __meltdown_safe = false;
862 * For reasons that aren't entirely clear, enabling KPTI on Cavium
863 * ThunderX leads to apparent I-cache corruption of kernel text, which
864 * ends as well as you might imagine. Don't even try.
866 if (cpus_have_const_cap(ARM64_WORKAROUND_CAVIUM_27456)) {
867 str = "ARM64_WORKAROUND_CAVIUM_27456";
871 /* Useful for KASLR robustness */
872 if (IS_ENABLED(CONFIG_RANDOMIZE_BASE) && kaslr_offset() > 0) {
873 if (!__kpti_forced) {
879 if (cpu_mitigations_off() && !__kpti_forced) {
880 str = "mitigations=off";
884 if (!IS_ENABLED(CONFIG_UNMAP_KERNEL_AT_EL0)) {
885 pr_info_once("kernel page table isolation disabled by kernel configuration\n");
891 pr_info_once("kernel page table isolation forced %s by %s\n",
892 __kpti_forced > 0 ? "ON" : "OFF", str);
893 return __kpti_forced > 0;
896 return !meltdown_safe;
899 #ifdef CONFIG_UNMAP_KERNEL_AT_EL0
901 kpti_install_ng_mappings(const struct arm64_cpu_capabilities *__unused)
903 typedef void (kpti_remap_fn)(int, int, phys_addr_t);
904 extern kpti_remap_fn idmap_kpti_install_ng_mappings;
905 kpti_remap_fn *remap_fn;
907 static bool kpti_applied = false;
908 int cpu = smp_processor_id();
910 if (__this_cpu_read(this_cpu_vector) == vectors) {
911 const char *v = arm64_get_bp_hardening_vector(EL1_VECTOR_KPTI);
913 __this_cpu_write(this_cpu_vector, v);
919 remap_fn = (void *)__pa_symbol(idmap_kpti_install_ng_mappings);
922 remap_fn(cpu, num_online_cpus(), __pa_symbol(swapper_pg_dir));
923 cpu_uninstall_idmap();
932 kpti_install_ng_mappings(const struct arm64_cpu_capabilities *__unused)
935 #endif /* CONFIG_UNMAP_KERNEL_AT_EL0 */
937 static int __init parse_kpti(char *str)
940 int ret = strtobool(str, &enabled);
945 __kpti_forced = enabled ? 1 : -1;
948 early_param("kpti", parse_kpti);
950 #ifdef CONFIG_ARM64_VHE
951 static bool runs_at_el2(const struct arm64_cpu_capabilities *entry, int __unused)
953 return is_kernel_in_hyp_mode();
956 static void cpu_copy_el2regs(const struct arm64_cpu_capabilities *__unused)
959 * Copy register values that aren't redirected by hardware.
961 * Before code patching, we only set tpidr_el1, all CPUs need to copy
962 * this value to tpidr_el2 before we patch the code. Once we've done
963 * that, freshly-onlined CPUs will set tpidr_el2, so we don't need to
966 if (!alternatives_applied)
967 write_sysreg(read_sysreg(tpidr_el1), tpidr_el2);
971 #ifdef CONFIG_ARM64_SSBD
972 static int ssbs_emulation_handler(struct pt_regs *regs, u32 instr)
977 if (instr & BIT(CRm_shift))
978 regs->pstate |= PSR_SSBS_BIT;
980 regs->pstate &= ~PSR_SSBS_BIT;
982 arm64_skip_faulting_instruction(regs, 4);
986 static struct undef_hook ssbs_emulation_hook = {
987 .instr_mask = ~(1U << CRm_shift),
988 .instr_val = 0xd500001f | REG_PSTATE_SSBS_IMM,
989 .fn = ssbs_emulation_handler,
992 static void cpu_enable_ssbs(const struct arm64_cpu_capabilities *__unused)
994 static bool undef_hook_registered = false;
995 static DEFINE_SPINLOCK(hook_lock);
997 spin_lock(&hook_lock);
998 if (!undef_hook_registered) {
999 register_undef_hook(&ssbs_emulation_hook);
1000 undef_hook_registered = true;
1002 spin_unlock(&hook_lock);
1004 if (arm64_get_ssbd_state() == ARM64_SSBD_FORCE_DISABLE) {
1005 sysreg_clear_set(sctlr_el1, 0, SCTLR_ELx_DSSBS);
1006 arm64_set_ssbd_mitigation(false);
1008 arm64_set_ssbd_mitigation(true);
1011 #endif /* CONFIG_ARM64_SSBD */
1013 static const struct arm64_cpu_capabilities arm64_features[] = {
1015 .desc = "GIC system register CPU interface",
1016 .capability = ARM64_HAS_SYSREG_GIC_CPUIF,
1017 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1018 .matches = has_useable_gicv3_cpuif,
1019 .sys_reg = SYS_ID_AA64PFR0_EL1,
1020 .field_pos = ID_AA64PFR0_GIC_SHIFT,
1021 .sign = FTR_UNSIGNED,
1022 .min_field_value = 1,
1024 #ifdef CONFIG_ARM64_PAN
1026 .desc = "Privileged Access Never",
1027 .capability = ARM64_HAS_PAN,
1028 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1029 .matches = has_cpuid_feature,
1030 .sys_reg = SYS_ID_AA64MMFR1_EL1,
1031 .field_pos = ID_AA64MMFR1_PAN_SHIFT,
1032 .sign = FTR_UNSIGNED,
1033 .min_field_value = 1,
1034 .cpu_enable = cpu_enable_pan,
1036 #endif /* CONFIG_ARM64_PAN */
1037 #if defined(CONFIG_AS_LSE) && defined(CONFIG_ARM64_LSE_ATOMICS)
1039 .desc = "LSE atomic instructions",
1040 .capability = ARM64_HAS_LSE_ATOMICS,
1041 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1042 .matches = has_cpuid_feature,
1043 .sys_reg = SYS_ID_AA64ISAR0_EL1,
1044 .field_pos = ID_AA64ISAR0_ATOMICS_SHIFT,
1045 .sign = FTR_UNSIGNED,
1046 .min_field_value = 2,
1048 #endif /* CONFIG_AS_LSE && CONFIG_ARM64_LSE_ATOMICS */
1050 .desc = "Software prefetching using PRFM",
1051 .capability = ARM64_HAS_NO_HW_PREFETCH,
1052 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE,
1053 .matches = has_no_hw_prefetch,
1055 #ifdef CONFIG_ARM64_UAO
1057 .desc = "User Access Override",
1058 .capability = ARM64_HAS_UAO,
1059 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1060 .matches = has_cpuid_feature,
1061 .sys_reg = SYS_ID_AA64MMFR2_EL1,
1062 .field_pos = ID_AA64MMFR2_UAO_SHIFT,
1063 .min_field_value = 1,
1065 * We rely on stop_machine() calling uao_thread_switch() to set
1066 * UAO immediately after patching.
1069 #endif /* CONFIG_ARM64_UAO */
1070 #ifdef CONFIG_ARM64_PAN
1072 .capability = ARM64_ALT_PAN_NOT_UAO,
1073 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1074 .matches = cpufeature_pan_not_uao,
1076 #endif /* CONFIG_ARM64_PAN */
1077 #ifdef CONFIG_ARM64_VHE
1079 .desc = "Virtualization Host Extensions",
1080 .capability = ARM64_HAS_VIRT_HOST_EXTN,
1081 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE,
1082 .matches = runs_at_el2,
1083 .cpu_enable = cpu_copy_el2regs,
1085 #endif /* CONFIG_ARM64_VHE */
1087 .desc = "32-bit EL0 Support",
1088 .capability = ARM64_HAS_32BIT_EL0,
1089 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1090 .matches = has_cpuid_feature,
1091 .sys_reg = SYS_ID_AA64PFR0_EL1,
1092 .sign = FTR_UNSIGNED,
1093 .field_pos = ID_AA64PFR0_EL0_SHIFT,
1094 .min_field_value = ID_AA64PFR0_EL0_32BIT_64BIT,
1097 .desc = "Reduced HYP mapping offset",
1098 .capability = ARM64_HYP_OFFSET_LOW,
1099 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1100 .matches = hyp_offset_low,
1103 .desc = "Kernel page table isolation (KPTI)",
1104 .capability = ARM64_UNMAP_KERNEL_AT_EL0,
1105 .type = ARM64_CPUCAP_BOOT_RESTRICTED_CPU_LOCAL_FEATURE,
1107 * The ID feature fields below are used to indicate that
1108 * the CPU doesn't need KPTI. See unmap_kernel_at_el0 for
1111 .sys_reg = SYS_ID_AA64PFR0_EL1,
1112 .field_pos = ID_AA64PFR0_CSV3_SHIFT,
1113 .min_field_value = 1,
1114 .matches = unmap_kernel_at_el0,
1115 .cpu_enable = kpti_install_ng_mappings,
1118 /* FP/SIMD is not implemented */
1119 .capability = ARM64_HAS_NO_FPSIMD,
1120 .type = ARM64_CPUCAP_BOOT_RESTRICTED_CPU_LOCAL_FEATURE,
1121 .min_field_value = 0,
1122 .matches = has_no_fpsimd,
1124 #ifdef CONFIG_ARM64_PMEM
1126 .desc = "Data cache clean to Point of Persistence",
1127 .capability = ARM64_HAS_DCPOP,
1128 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1129 .matches = has_cpuid_feature,
1130 .sys_reg = SYS_ID_AA64ISAR1_EL1,
1131 .field_pos = ID_AA64ISAR1_DPB_SHIFT,
1132 .min_field_value = 1,
1135 #ifdef CONFIG_ARM64_SSBD
1137 .desc = "Speculative Store Bypassing Safe (SSBS)",
1138 .capability = ARM64_SSBS,
1139 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE,
1140 .matches = has_cpuid_feature,
1141 .sys_reg = SYS_ID_AA64PFR1_EL1,
1142 .field_pos = ID_AA64PFR1_SSBS_SHIFT,
1143 .sign = FTR_UNSIGNED,
1144 .min_field_value = ID_AA64PFR1_SSBS_PSTATE_ONLY,
1145 .cpu_enable = cpu_enable_ssbs,
1152 #define HWCAP_CPUID_MATCH(reg, field, s, min_value) \
1153 .matches = has_cpuid_feature, \
1155 .field_pos = field, \
1157 .min_field_value = min_value, \
1159 #define __HWCAP_CAP(name, cap_type, cap) \
1161 .type = ARM64_CPUCAP_SYSTEM_FEATURE, \
1162 .hwcap_type = cap_type, \
1165 #define HWCAP_CAP(reg, field, s, min_value, cap_type, cap) \
1167 __HWCAP_CAP(#cap, cap_type, cap) \
1168 HWCAP_CPUID_MATCH(reg, field, s, min_value) \
1171 #define HWCAP_CAP_MATCH(match, cap_type, cap) \
1173 __HWCAP_CAP(#cap, cap_type, cap) \
1177 static const struct arm64_cpu_capabilities arm64_elf_hwcaps[] = {
1178 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_AES_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, HWCAP_PMULL),
1179 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_AES_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_AES),
1180 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA1_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_SHA1),
1181 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA2_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_SHA2),
1182 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA2_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, HWCAP_SHA512),
1183 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_CRC32_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_CRC32),
1184 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_ATOMICS_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, HWCAP_ATOMICS),
1185 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_RDM_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_ASIMDRDM),
1186 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA3_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_SHA3),
1187 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SM3_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_SM3),
1188 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SM4_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_SM4),
1189 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_DP_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_ASIMDDP),
1190 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_FHM_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_ASIMDFHM),
1191 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_TS_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_FLAGM),
1192 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_FP_SHIFT, FTR_SIGNED, 0, CAP_HWCAP, HWCAP_FP),
1193 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_FP_SHIFT, FTR_SIGNED, 1, CAP_HWCAP, HWCAP_FPHP),
1194 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_ASIMD_SHIFT, FTR_SIGNED, 0, CAP_HWCAP, HWCAP_ASIMD),
1195 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_ASIMD_SHIFT, FTR_SIGNED, 1, CAP_HWCAP, HWCAP_ASIMDHP),
1196 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_DIT_SHIFT, FTR_SIGNED, 1, CAP_HWCAP, HWCAP_DIT),
1197 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_DPB_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_DCPOP),
1198 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_JSCVT_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_JSCVT),
1199 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_FCMA_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_FCMA),
1200 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_LRCPC_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_LRCPC),
1201 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_LRCPC_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, HWCAP_ILRCPC),
1202 HWCAP_CAP(SYS_ID_AA64MMFR2_EL1, ID_AA64MMFR2_AT_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_USCAT),
1203 HWCAP_CAP(SYS_ID_AA64PFR1_EL1, ID_AA64PFR1_SSBS_SHIFT, FTR_UNSIGNED, ID_AA64PFR1_SSBS_PSTATE_INSNS, CAP_HWCAP, HWCAP_SSBS),
1207 #ifdef CONFIG_COMPAT
1208 static bool compat_has_neon(const struct arm64_cpu_capabilities *cap, int scope)
1211 * Check that all of MVFR1_EL1.{SIMDSP, SIMDInt, SIMDLS} are available,
1212 * in line with that of arm32 as in vfp_init(). We make sure that the
1213 * check is future proof, by making sure value is non-zero.
1217 WARN_ON(scope == SCOPE_LOCAL_CPU && preemptible());
1218 if (scope == SCOPE_SYSTEM)
1219 mvfr1 = read_sanitised_ftr_reg(SYS_MVFR1_EL1);
1221 mvfr1 = read_sysreg_s(SYS_MVFR1_EL1);
1223 return cpuid_feature_extract_unsigned_field(mvfr1, MVFR1_SIMDSP_SHIFT) &&
1224 cpuid_feature_extract_unsigned_field(mvfr1, MVFR1_SIMDINT_SHIFT) &&
1225 cpuid_feature_extract_unsigned_field(mvfr1, MVFR1_SIMDLS_SHIFT);
1229 static const struct arm64_cpu_capabilities compat_elf_hwcaps[] = {
1230 #ifdef CONFIG_COMPAT
1231 HWCAP_CAP_MATCH(compat_has_neon, CAP_COMPAT_HWCAP, COMPAT_HWCAP_NEON),
1232 HWCAP_CAP(SYS_MVFR1_EL1, MVFR1_SIMDFMAC_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP, COMPAT_HWCAP_VFPv4),
1233 /* Arm v8 mandates MVFR0.FPDP == {0, 2}. So, piggy back on this for the presence of VFP support */
1234 HWCAP_CAP(SYS_MVFR0_EL1, MVFR0_FPDP_SHIFT, FTR_UNSIGNED, 2, CAP_COMPAT_HWCAP, COMPAT_HWCAP_VFP),
1235 HWCAP_CAP(SYS_MVFR0_EL1, MVFR0_FPDP_SHIFT, FTR_UNSIGNED, 2, CAP_COMPAT_HWCAP, COMPAT_HWCAP_VFPv3),
1236 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_AES_SHIFT, FTR_UNSIGNED, 2, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_PMULL),
1237 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_AES_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_AES),
1238 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_SHA1_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA1),
1239 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_SHA2_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA2),
1240 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_CRC32_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_CRC32),
1245 static void __init cap_set_elf_hwcap(const struct arm64_cpu_capabilities *cap)
1247 switch (cap->hwcap_type) {
1249 elf_hwcap |= cap->hwcap;
1251 #ifdef CONFIG_COMPAT
1252 case CAP_COMPAT_HWCAP:
1253 compat_elf_hwcap |= (u32)cap->hwcap;
1255 case CAP_COMPAT_HWCAP2:
1256 compat_elf_hwcap2 |= (u32)cap->hwcap;
1265 /* Check if we have a particular HWCAP enabled */
1266 static bool cpus_have_elf_hwcap(const struct arm64_cpu_capabilities *cap)
1270 switch (cap->hwcap_type) {
1272 rc = (elf_hwcap & cap->hwcap) != 0;
1274 #ifdef CONFIG_COMPAT
1275 case CAP_COMPAT_HWCAP:
1276 rc = (compat_elf_hwcap & (u32)cap->hwcap) != 0;
1278 case CAP_COMPAT_HWCAP2:
1279 rc = (compat_elf_hwcap2 & (u32)cap->hwcap) != 0;
1290 static void __init setup_elf_hwcaps(const struct arm64_cpu_capabilities *hwcaps)
1292 /* We support emulation of accesses to CPU ID feature registers */
1293 elf_hwcap |= HWCAP_CPUID;
1294 for (; hwcaps->matches; hwcaps++)
1295 if (hwcaps->matches(hwcaps, cpucap_default_scope(hwcaps)))
1296 cap_set_elf_hwcap(hwcaps);
1300 * Check if the current CPU has a given feature capability.
1301 * Should be called from non-preemptible context.
1303 static bool __this_cpu_has_cap(const struct arm64_cpu_capabilities *cap_array,
1306 const struct arm64_cpu_capabilities *caps;
1308 if (WARN_ON(preemptible()))
1311 for (caps = cap_array; caps->matches; caps++)
1312 if (caps->capability == cap &&
1313 caps->matches(caps, SCOPE_LOCAL_CPU))
1318 static void __update_cpu_capabilities(const struct arm64_cpu_capabilities *caps,
1319 u16 scope_mask, const char *info)
1321 scope_mask &= ARM64_CPUCAP_SCOPE_MASK;
1322 for (; caps->matches; caps++) {
1323 if (!(caps->type & scope_mask) ||
1324 !caps->matches(caps, cpucap_default_scope(caps)))
1327 if (!cpus_have_cap(caps->capability) && caps->desc)
1328 pr_info("%s %s\n", info, caps->desc);
1329 cpus_set_cap(caps->capability);
1333 static void update_cpu_capabilities(u16 scope_mask)
1335 __update_cpu_capabilities(arm64_errata, scope_mask,
1336 "enabling workaround for");
1337 __update_cpu_capabilities(arm64_features, scope_mask, "detected:");
1340 static int __enable_cpu_capability(void *arg)
1342 const struct arm64_cpu_capabilities *cap = arg;
1344 cap->cpu_enable(cap);
1349 * Run through the enabled capabilities and enable() it on all active
1353 __enable_cpu_capabilities(const struct arm64_cpu_capabilities *caps,
1356 scope_mask &= ARM64_CPUCAP_SCOPE_MASK;
1357 for (; caps->matches; caps++) {
1358 unsigned int num = caps->capability;
1360 if (!(caps->type & scope_mask) || !cpus_have_cap(num))
1363 /* Ensure cpus_have_const_cap(num) works */
1364 static_branch_enable(&cpu_hwcap_keys[num]);
1366 if (caps->cpu_enable) {
1368 * Capabilities with SCOPE_BOOT_CPU scope are finalised
1369 * before any secondary CPU boots. Thus, each secondary
1370 * will enable the capability as appropriate via
1371 * check_local_cpu_capabilities(). The only exception is
1372 * the boot CPU, for which the capability must be
1373 * enabled here. This approach avoids costly
1374 * stop_machine() calls for this case.
1376 * Otherwise, use stop_machine() as it schedules the
1377 * work allowing us to modify PSTATE, instead of
1378 * on_each_cpu() which uses an IPI, giving us a PSTATE
1379 * that disappears when we return.
1381 if (scope_mask & SCOPE_BOOT_CPU)
1382 caps->cpu_enable(caps);
1384 stop_machine(__enable_cpu_capability,
1385 (void *)caps, cpu_online_mask);
1390 static void __init enable_cpu_capabilities(u16 scope_mask)
1392 __enable_cpu_capabilities(arm64_errata, scope_mask);
1393 __enable_cpu_capabilities(arm64_features, scope_mask);
1397 * Flag to indicate if we have computed the system wide
1398 * capabilities based on the boot time active CPUs. This
1399 * will be used to determine if a new booting CPU should
1400 * go through the verification process to make sure that it
1401 * supports the system capabilities, without using a hotplug
1404 static bool sys_caps_initialised;
1406 static inline void set_sys_caps_initialised(void)
1408 sys_caps_initialised = true;
1412 * Run through the list of capabilities to check for conflicts.
1413 * If the system has already detected a capability, take necessary
1414 * action on this CPU.
1416 * Returns "false" on conflicts.
1419 __verify_local_cpu_caps(const struct arm64_cpu_capabilities *caps_list,
1422 bool cpu_has_cap, system_has_cap;
1423 const struct arm64_cpu_capabilities *caps;
1425 scope_mask &= ARM64_CPUCAP_SCOPE_MASK;
1427 for (caps = caps_list; caps->matches; caps++) {
1428 if (!(caps->type & scope_mask))
1431 cpu_has_cap = __this_cpu_has_cap(caps_list, caps->capability);
1432 system_has_cap = cpus_have_cap(caps->capability);
1434 if (system_has_cap) {
1436 * Check if the new CPU misses an advertised feature,
1437 * which is not safe to miss.
1439 if (!cpu_has_cap && !cpucap_late_cpu_optional(caps))
1442 * We have to issue cpu_enable() irrespective of
1443 * whether the CPU has it or not, as it is enabeld
1444 * system wide. It is upto the call back to take
1445 * appropriate action on this CPU.
1447 if (caps->cpu_enable)
1448 caps->cpu_enable(caps);
1451 * Check if the CPU has this capability if it isn't
1452 * safe to have when the system doesn't.
1454 if (cpu_has_cap && !cpucap_late_cpu_permitted(caps))
1459 if (caps->matches) {
1460 pr_crit("CPU%d: Detected conflict for capability %d (%s), System: %d, CPU: %d\n",
1461 smp_processor_id(), caps->capability,
1462 caps->desc, system_has_cap, cpu_has_cap);
1469 static bool verify_local_cpu_caps(u16 scope_mask)
1471 return __verify_local_cpu_caps(arm64_errata, scope_mask) &&
1472 __verify_local_cpu_caps(arm64_features, scope_mask);
1476 * Check for CPU features that are used in early boot
1477 * based on the Boot CPU value.
1479 static void check_early_cpu_features(void)
1481 verify_cpu_asid_bits();
1483 * Early features are used by the kernel already. If there
1484 * is a conflict, we cannot proceed further.
1486 if (!verify_local_cpu_caps(SCOPE_BOOT_CPU))
1491 verify_local_elf_hwcaps(const struct arm64_cpu_capabilities *caps)
1494 for (; caps->matches; caps++)
1495 if (cpus_have_elf_hwcap(caps) && !caps->matches(caps, SCOPE_LOCAL_CPU)) {
1496 pr_crit("CPU%d: missing HWCAP: %s\n",
1497 smp_processor_id(), caps->desc);
1504 * Run through the enabled system capabilities and enable() it on this CPU.
1505 * The capabilities were decided based on the available CPUs at the boot time.
1506 * Any new CPU should match the system wide status of the capability. If the
1507 * new CPU doesn't have a capability which the system now has enabled, we
1508 * cannot do anything to fix it up and could cause unexpected failures. So
1511 static void verify_local_cpu_capabilities(void)
1514 * The capabilities with SCOPE_BOOT_CPU are checked from
1515 * check_early_cpu_features(), as they need to be verified
1516 * on all secondary CPUs.
1518 if (!verify_local_cpu_caps(SCOPE_ALL & ~SCOPE_BOOT_CPU))
1521 verify_local_elf_hwcaps(arm64_elf_hwcaps);
1522 if (system_supports_32bit_el0())
1523 verify_local_elf_hwcaps(compat_elf_hwcaps);
1526 void check_local_cpu_capabilities(void)
1529 * All secondary CPUs should conform to the early CPU features
1530 * in use by the kernel based on boot CPU.
1532 check_early_cpu_features();
1535 * If we haven't finalised the system capabilities, this CPU gets
1536 * a chance to update the errata work arounds and local features.
1537 * Otherwise, this CPU should verify that it has all the system
1538 * advertised capabilities.
1540 if (!sys_caps_initialised)
1541 update_cpu_capabilities(SCOPE_LOCAL_CPU);
1543 verify_local_cpu_capabilities();
1546 static void __init setup_boot_cpu_capabilities(void)
1548 /* Detect capabilities with either SCOPE_BOOT_CPU or SCOPE_LOCAL_CPU */
1549 update_cpu_capabilities(SCOPE_BOOT_CPU | SCOPE_LOCAL_CPU);
1550 /* Enable the SCOPE_BOOT_CPU capabilities alone right away */
1551 enable_cpu_capabilities(SCOPE_BOOT_CPU);
1554 DEFINE_STATIC_KEY_FALSE(arm64_const_caps_ready);
1555 EXPORT_SYMBOL(arm64_const_caps_ready);
1557 static void __init mark_const_caps_ready(void)
1559 static_branch_enable(&arm64_const_caps_ready);
1562 extern const struct arm64_cpu_capabilities arm64_errata[];
1564 bool this_cpu_has_cap(unsigned int cap)
1566 return (__this_cpu_has_cap(arm64_features, cap) ||
1567 __this_cpu_has_cap(arm64_errata, cap));
1570 static void __init setup_system_capabilities(void)
1573 * We have finalised the system-wide safe feature
1574 * registers, finalise the capabilities that depend
1575 * on it. Also enable all the available capabilities,
1576 * that are not enabled already.
1578 update_cpu_capabilities(SCOPE_SYSTEM);
1579 enable_cpu_capabilities(SCOPE_ALL & ~SCOPE_BOOT_CPU);
1582 void __init setup_cpu_features(void)
1587 setup_system_capabilities();
1588 mark_const_caps_ready();
1589 setup_elf_hwcaps(arm64_elf_hwcaps);
1591 if (system_supports_32bit_el0())
1592 setup_elf_hwcaps(compat_elf_hwcaps);
1594 /* Advertise that we have computed the system capabilities */
1595 set_sys_caps_initialised();
1598 * Check for sane CTR_EL0.CWG value.
1600 cwg = cache_type_cwg();
1601 cls = cache_line_size();
1603 pr_warn("No Cache Writeback Granule information, assuming cache line size %d\n",
1605 if (L1_CACHE_BYTES < cls)
1606 pr_warn("L1_CACHE_BYTES smaller than the Cache Writeback Granule (%d < %d)\n",
1607 L1_CACHE_BYTES, cls);
1610 static bool __maybe_unused
1611 cpufeature_pan_not_uao(const struct arm64_cpu_capabilities *entry, int __unused)
1613 return (cpus_have_const_cap(ARM64_HAS_PAN) && !cpus_have_const_cap(ARM64_HAS_UAO));
1617 * We emulate only the following system register space.
1618 * Op0 = 0x3, CRn = 0x0, Op1 = 0x0, CRm = [0, 4 - 7]
1619 * See Table C5-6 System instruction encodings for System register accesses,
1620 * ARMv8 ARM(ARM DDI 0487A.f) for more details.
1622 static inline bool __attribute_const__ is_emulated(u32 id)
1624 return (sys_reg_Op0(id) == 0x3 &&
1625 sys_reg_CRn(id) == 0x0 &&
1626 sys_reg_Op1(id) == 0x0 &&
1627 (sys_reg_CRm(id) == 0 ||
1628 ((sys_reg_CRm(id) >= 4) && (sys_reg_CRm(id) <= 7))));
1632 * With CRm == 0, reg should be one of :
1633 * MIDR_EL1, MPIDR_EL1 or REVIDR_EL1.
1635 static inline int emulate_id_reg(u32 id, u64 *valp)
1639 *valp = read_cpuid_id();
1642 *valp = SYS_MPIDR_SAFE_VAL;
1644 case SYS_REVIDR_EL1:
1645 /* IMPLEMENTATION DEFINED values are emulated with 0 */
1655 static int emulate_sys_reg(u32 id, u64 *valp)
1657 struct arm64_ftr_reg *regp;
1659 if (!is_emulated(id))
1662 if (sys_reg_CRm(id) == 0)
1663 return emulate_id_reg(id, valp);
1665 regp = get_arm64_ftr_reg(id);
1667 *valp = arm64_ftr_reg_user_value(regp);
1670 * The untracked registers are either IMPLEMENTATION DEFINED
1671 * (e.g, ID_AFR0_EL1) or reserved RAZ.
1677 static int emulate_mrs(struct pt_regs *regs, u32 insn)
1684 * sys_reg values are defined as used in mrs/msr instruction.
1685 * shift the imm value to get the encoding.
1687 sys_reg = (u32)aarch64_insn_decode_immediate(AARCH64_INSN_IMM_16, insn) << 5;
1688 rc = emulate_sys_reg(sys_reg, &val);
1690 dst = aarch64_insn_decode_register(AARCH64_INSN_REGTYPE_RT, insn);
1691 pt_regs_write_reg(regs, dst, val);
1692 arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE);
1698 static struct undef_hook mrs_hook = {
1699 .instr_mask = 0xfff00000,
1700 .instr_val = 0xd5300000,
1701 .pstate_mask = COMPAT_PSR_MODE_MASK,
1702 .pstate_val = PSR_MODE_EL0t,
1706 static int __init enable_mrs_emulation(void)
1708 register_undef_hook(&mrs_hook);
1712 core_initcall(enable_mrs_emulation);
1714 ssize_t cpu_show_meltdown(struct device *dev, struct device_attribute *attr,
1717 if (__meltdown_safe)
1718 return sprintf(buf, "Not affected\n");
1720 if (arm64_kernel_unmapped_at_el0())
1721 return sprintf(buf, "Mitigation: PTI\n");
1723 return sprintf(buf, "Vulnerable\n");