1 # SPDX-License-Identifier: GPL-2.0
4 $id: http://devicetree.org/schemas/arm/arm,cci-400.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ARM CCI Cache Coherent Interconnect
10 - Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
13 ARM multi-cluster systems maintain intra-cluster coherency through a cache
14 coherent interconnect (CCI) that is capable of monitoring bus transactions
15 and manage coherency, TLB invalidations and memory barriers.
17 It allows snooping and distributed virtual memory message broadcast across
18 clusters, through memory mapped interface, with a global control register
19 space and multiple sets of interface control registers, one per slave
24 pattern: "^cci(@[0-9a-f]+)?$"
35 Specifies base physical address of CCI control registers common to all
38 "#address-cells": true
43 "^slave-if@[0-9a-f]+$":
48 const: arm,cci-400-ctrl-if
63 additionalProperties: false
71 - const: arm,cci-400-pmu,r0
72 - const: arm,cci-400-pmu,r1
73 - const: arm,cci-400-pmu
76 Permitted only where OS has secure access to CCI registers
77 - const: arm,cci-500-pmu,r0
78 - const: arm,cci-550-pmu,r0
84 List of counter overflow interrupts, one per counter. The interrupts
85 must be specified starting with the cycle counter overflow interrupt,
86 followed by counter0 overflow interrupt, counter1 overflow
87 interrupt,... ,counterN overflow interrupt.
89 The CCI PMU has an interrupt signal for each counter. The number of
90 interrupts must be equal to the number of counters.
100 additionalProperties: false
109 additionalProperties: false
114 #address-cells = <2>;
117 compatible = "arm,vexpress,v2p-ca15_a7", "arm,vexpress";
118 model = "V2P-CA15_CA7";
120 interrupt-parent = <&gic>;
122 gic: interrupt-controller {
123 interrupt-controller;
124 #interrupt-cells = <3>;
128 * This CCI node corresponds to a CCI component whose control
129 * registers sits at address 0x000000002c090000.
131 * CCI slave interface @0x000000002c091000 is connected to dma
134 * CCI slave interface @0x000000002c094000 is connected to CPUs
137 * CCI slave interface @0x000000002c095000 is connected to CPUs
143 #address-cells = <1>;
147 compatible = "arm,cortex-a15";
148 cci-control-port = <&cci_control1>;
154 compatible = "arm,cortex-a15";
155 cci-control-port = <&cci_control1>;
161 compatible = "arm,cortex-a7";
162 cci-control-port = <&cci_control2>;
168 compatible = "arm,cortex-a7";
169 cci-control-port = <&cci_control2>;
175 compatible = "arm,cci-400";
176 #address-cells = <1>;
178 reg = <0x0 0x2c090000 0 0x1000>;
179 ranges = <0x0 0x0 0x2c090000 0x10000>;
181 cci_control0: slave-if@1000 {
182 compatible = "arm,cci-400-ctrl-if";
183 interface-type = "ace-lite";
184 reg = <0x1000 0x1000>;
187 cci_control1: slave-if@4000 {
188 compatible = "arm,cci-400-ctrl-if";
189 interface-type = "ace";
190 reg = <0x4000 0x1000>;
193 cci_control2: slave-if@5000 {
194 compatible = "arm,cci-400-ctrl-if";
195 interface-type = "ace";
196 reg = <0x5000 0x1000>;
200 compatible = "arm,cci-400-pmu";
201 reg = <0x9000 0x5000>;
202 interrupts = <0 101 4>,