2 * arch/xtensa/kernel/setup.c
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file "COPYING" in the main directory of this archive
8 * Copyright (C) 1995 Linus Torvalds
9 * Copyright (C) 2001 - 2005 Tensilica Inc.
10 * Copyright (C) 2014 - 2016 Cadence Design Systems Inc.
12 * Chris Zankel <chris@zankel.net>
13 * Joe Taylor <joe@tensilica.com, joetylr@yahoo.com>
15 * Marc Gauthier<marc@tensilica.com> <marc@alumni.uwaterloo.ca>
18 #include <linux/errno.h>
19 #include <linux/init.h>
21 #include <linux/proc_fs.h>
22 #include <linux/kernel.h>
23 #include <linux/percpu.h>
24 #include <linux/reboot.h>
25 #include <linux/cpu.h>
27 #include <linux/of_fdt.h>
29 #if defined(CONFIG_VGA_CONSOLE) || defined(CONFIG_DUMMY_CONSOLE)
30 # include <linux/console.h>
34 # include <linux/seq_file.h>
37 #include <asm/bootparam.h>
38 #include <asm/kasan.h>
39 #include <asm/mmu_context.h>
41 #include <asm/param.h>
42 #include <asm/platform.h>
43 #include <asm/processor.h>
44 #include <asm/sections.h>
45 #include <asm/setup.h>
47 #include <asm/sysmem.h>
48 #include <asm/timex.h>
49 #include <asm/traps.h>
51 #ifdef CONFIG_BLK_DEV_INITRD
52 extern unsigned long initrd_start;
53 extern unsigned long initrd_end;
54 extern int initrd_below_start_ok;
58 void *dtb_start = __dtb_start;
61 extern unsigned long loops_per_jiffy;
63 /* Command line specified as configuration option. */
65 static char __initdata command_line[COMMAND_LINE_SIZE];
67 #ifdef CONFIG_CMDLINE_BOOL
68 static char default_command_line[COMMAND_LINE_SIZE] __initdata = CONFIG_CMDLINE;
71 #ifdef CONFIG_PARSE_BOOTPARAM
73 * Boot parameter parsing.
75 * The Xtensa port uses a list of variable-sized tags to pass data to
76 * the kernel. The first tag must be a BP_TAG_FIRST tag for the list
77 * to be recognised. The list is terminated with a zero-sized
81 typedef struct tagtable {
83 int (*parse)(const bp_tag_t*);
86 #define __tagtable(tag, fn) static tagtable_t __tagtable_##fn \
87 __section(".taglist") __attribute__((used)) = { tag, fn }
89 /* parse current tag */
91 static int __init parse_tag_mem(const bp_tag_t *tag)
93 struct bp_meminfo *mi = (struct bp_meminfo *)(tag->data);
95 if (mi->type != MEMORY_TYPE_CONVENTIONAL)
98 return memblock_add(mi->start, mi->end - mi->start);
101 __tagtable(BP_TAG_MEMORY, parse_tag_mem);
103 #ifdef CONFIG_BLK_DEV_INITRD
105 static int __init parse_tag_initrd(const bp_tag_t* tag)
107 struct bp_meminfo *mi = (struct bp_meminfo *)(tag->data);
109 initrd_start = (unsigned long)__va(mi->start);
110 initrd_end = (unsigned long)__va(mi->end);
115 __tagtable(BP_TAG_INITRD, parse_tag_initrd);
117 #endif /* CONFIG_BLK_DEV_INITRD */
121 static int __init parse_tag_fdt(const bp_tag_t *tag)
123 dtb_start = __va(tag->data[0]);
127 __tagtable(BP_TAG_FDT, parse_tag_fdt);
129 #endif /* CONFIG_USE_OF */
131 static int __init parse_tag_cmdline(const bp_tag_t* tag)
133 strscpy(command_line, (char *)(tag->data), COMMAND_LINE_SIZE);
137 __tagtable(BP_TAG_COMMAND_LINE, parse_tag_cmdline);
139 static int __init parse_bootparam(const bp_tag_t* tag)
141 extern tagtable_t __tagtable_begin, __tagtable_end;
144 /* Boot parameters must start with a BP_TAG_FIRST tag. */
146 if (tag->id != BP_TAG_FIRST) {
147 pr_warn("Invalid boot parameters!\n");
151 tag = (bp_tag_t*)((unsigned long)tag + sizeof(bp_tag_t) + tag->size);
153 /* Parse all tags. */
155 while (tag != NULL && tag->id != BP_TAG_LAST) {
156 for (t = &__tagtable_begin; t < &__tagtable_end; t++) {
157 if (tag->id == t->tag) {
162 if (t == &__tagtable_end)
163 pr_warn("Ignoring tag 0x%08x\n", tag->id);
164 tag = (bp_tag_t*)((unsigned long)(tag + 1) + tag->size);
170 static int __init parse_bootparam(const bp_tag_t *tag)
172 pr_info("Ignoring boot parameters at %p\n", tag);
179 #if !XCHAL_HAVE_PTP_MMU || XCHAL_HAVE_SPANNING_WAY
180 unsigned long xtensa_kio_paddr = XCHAL_KIO_DEFAULT_PADDR;
181 EXPORT_SYMBOL(xtensa_kio_paddr);
183 static int __init xtensa_dt_io_area(unsigned long node, const char *uname,
184 int depth, void *data)
186 const __be32 *ranges;
192 if (!of_flat_dt_is_compatible(node, "simple-bus"))
195 ranges = of_get_flat_dt_prop(node, "ranges", &len);
201 xtensa_kio_paddr = of_read_ulong(ranges+1, 1);
202 /* round down to nearest 256MB boundary */
203 xtensa_kio_paddr &= 0xf0000000;
210 static int __init xtensa_dt_io_area(unsigned long node, const char *uname,
211 int depth, void *data)
217 void __init early_init_devtree(void *params)
219 early_init_dt_scan(params);
220 of_scan_flat_dt(xtensa_dt_io_area, NULL);
222 if (!command_line[0])
223 strscpy(command_line, boot_command_line, COMMAND_LINE_SIZE);
226 #endif /* CONFIG_USE_OF */
229 * Initialize architecture. (Early stage)
232 void __init init_arch(bp_tag_t *bp_start)
234 /* Initialize basic exception handling if configuration may need it */
236 if (IS_ENABLED(CONFIG_KASAN) ||
237 IS_ENABLED(CONFIG_XTENSA_LOAD_STORE))
240 /* Initialize MMU. */
244 /* Initialize initial KASAN shadow map */
248 /* Parse boot parameters */
251 parse_bootparam(bp_start);
254 early_init_devtree(dtb_start);
257 #ifdef CONFIG_CMDLINE_BOOL
258 if (!command_line[0])
259 strscpy(command_line, default_command_line, COMMAND_LINE_SIZE);
262 /* Early hook for platforms */
264 platform_init(bp_start);
268 * Initialize system. Setup memory and reserve regions.
271 static inline int __init_memblock mem_reserve(unsigned long start,
274 return memblock_reserve(start, end - start);
277 void __init setup_arch(char **cmdline_p)
279 pr_info("config ID: %08x:%08x\n",
280 xtensa_get_sr(SREG_EPC), xtensa_get_sr(SREG_EXCSAVE));
281 if (xtensa_get_sr(SREG_EPC) != XCHAL_HW_CONFIGID0 ||
282 xtensa_get_sr(SREG_EXCSAVE) != XCHAL_HW_CONFIGID1)
283 pr_info("built for config ID: %08x:%08x\n",
284 XCHAL_HW_CONFIGID0, XCHAL_HW_CONFIGID1);
286 *cmdline_p = command_line;
287 platform_setup(cmdline_p);
288 strscpy(boot_command_line, *cmdline_p, COMMAND_LINE_SIZE);
290 /* Reserve some memory regions */
292 #ifdef CONFIG_BLK_DEV_INITRD
293 if (initrd_start < initrd_end &&
294 !mem_reserve(__pa(initrd_start), __pa(initrd_end)))
295 initrd_below_start_ok = 1;
300 mem_reserve(__pa(_stext), __pa(_end));
301 #ifdef CONFIG_XIP_KERNEL
302 #ifdef CONFIG_VECTORS_ADDR
303 mem_reserve(__pa(_xip_text_start), __pa(_xip_text_end));
305 mem_reserve(__pa(_xip_start), __pa(_xip_end));
308 #ifdef CONFIG_VECTORS_ADDR
309 #ifdef SUPPORT_WINDOWED
310 mem_reserve(__pa(_WindowVectors_text_start),
311 __pa(_WindowVectors_text_end));
314 mem_reserve(__pa(_DebugInterruptVector_text_start),
315 __pa(_DebugInterruptVector_text_end));
317 mem_reserve(__pa(_KernelExceptionVector_text_start),
318 __pa(_KernelExceptionVector_text_end));
320 mem_reserve(__pa(_UserExceptionVector_text_start),
321 __pa(_UserExceptionVector_text_end));
323 mem_reserve(__pa(_DoubleExceptionVector_text_start),
324 __pa(_DoubleExceptionVector_text_end));
326 mem_reserve(__pa(_exception_text_start),
327 __pa(_exception_text_end));
328 #if XCHAL_EXCM_LEVEL >= 2
329 mem_reserve(__pa(_Level2InterruptVector_text_start),
330 __pa(_Level2InterruptVector_text_end));
332 #if XCHAL_EXCM_LEVEL >= 3
333 mem_reserve(__pa(_Level3InterruptVector_text_start),
334 __pa(_Level3InterruptVector_text_end));
336 #if XCHAL_EXCM_LEVEL >= 4
337 mem_reserve(__pa(_Level4InterruptVector_text_start),
338 __pa(_Level4InterruptVector_text_end));
340 #if XCHAL_EXCM_LEVEL >= 5
341 mem_reserve(__pa(_Level5InterruptVector_text_start),
342 __pa(_Level5InterruptVector_text_end));
344 #if XCHAL_EXCM_LEVEL >= 6
345 mem_reserve(__pa(_Level6InterruptVector_text_start),
346 __pa(_Level6InterruptVector_text_end));
349 #endif /* CONFIG_VECTORS_ADDR */
351 #ifdef CONFIG_SECONDARY_RESET_VECTOR
352 mem_reserve(__pa(_SecondaryResetVector_text_start),
353 __pa(_SecondaryResetVector_text_end));
358 unflatten_and_copy_device_tree();
368 # if defined(CONFIG_VGA_CONSOLE)
369 conswitchp = &vga_con;
374 static DEFINE_PER_CPU(struct cpu, cpu_data);
376 static int __init topology_init(void)
380 for_each_possible_cpu(i) {
381 struct cpu *cpu = &per_cpu(cpu_data, i);
382 cpu->hotpluggable = !!i;
383 register_cpu(cpu, i);
388 subsys_initcall(topology_init);
392 #if XCHAL_HAVE_PTP_MMU && IS_ENABLED(CONFIG_MMU)
395 * We have full MMU: all autoload ways, ways 7, 8 and 9 of DTLB must
397 * Way 4 is not currently used by linux.
398 * Ways 5 and 6 shall not be touched on MMUv2 as they are hardwired.
399 * Way 5 shall be flushed and way 6 shall be set to identity mapping
402 local_flush_tlb_all();
403 invalidate_page_directory();
404 #if XCHAL_HAVE_SPANNING_WAY
407 unsigned long vaddr = (unsigned long)cpu_reset;
408 unsigned long paddr = __pa(vaddr);
409 unsigned long tmpaddr = vaddr + SZ_512M;
410 unsigned long tmp0, tmp1, tmp2, tmp3;
413 * Find a place for the temporary mapping. It must not be
414 * in the same 512MB region with vaddr or paddr, otherwise
415 * there may be multihit exception either on entry to the
416 * temporary mapping, or on entry to the identity mapping.
417 * (512MB is the biggest page size supported by TLB.)
419 while (((tmpaddr ^ paddr) & -SZ_512M) == 0)
422 /* Invalidate mapping in the selected temporary area */
423 if (itlb_probe(tmpaddr) & BIT(ITLB_HIT_BIT))
424 invalidate_itlb_entry(itlb_probe(tmpaddr));
425 if (itlb_probe(tmpaddr + PAGE_SIZE) & BIT(ITLB_HIT_BIT))
426 invalidate_itlb_entry(itlb_probe(tmpaddr + PAGE_SIZE));
429 * Map two consecutive pages starting at the physical address
430 * of this function to the temporary mapping area.
432 write_itlb_entry(__pte((paddr & PAGE_MASK) |
436 tmpaddr & PAGE_MASK);
437 write_itlb_entry(__pte(((paddr & PAGE_MASK) + PAGE_SIZE) |
441 (tmpaddr & PAGE_MASK) + PAGE_SIZE);
443 /* Reinitialize TLB */
444 __asm__ __volatile__ ("movi %0, 1f\n\t"
450 * No literal, data or stack access
454 /* Initialize *tlbcfg */
456 "wsr %0, itlbcfg\n\t"
457 "wsr %0, dtlbcfg\n\t"
458 /* Invalidate TLB way 5 */
465 "addi %0, %0, -1\n\t"
467 /* Initialize TLB way 6 */
476 "addi %0, %0, -1\n\t"
479 /* Jump to identity mapping */
482 /* Complete way 6 initialization */
485 /* Invalidate temporary mapping */
490 : "=&a"(tmp0), "=&a"(tmp1), "=&a"(tmp2),
492 : "a"(tmpaddr - vaddr),
494 "a"(SZ_128M), "a"(SZ_512M),
496 "a"((tmpaddr + SZ_512M) & PAGE_MASK)
501 __asm__ __volatile__ ("movi a2, 0\n\t"
502 "wsr a2, icountlevel\n\t"
505 #if XCHAL_NUM_IBREAK > 0
506 "wsr a2, ibreakenable\n\t"
516 : "a" (XCHAL_RESET_VECTOR_VADDR)
522 void machine_restart(char * cmd)
526 do_kernel_restart(cmd);
527 pr_err("Reboot failed -- System halted\n");
532 void machine_halt(void)
536 do_kernel_power_off();
541 void machine_power_off(void)
545 do_kernel_power_off();
549 #ifdef CONFIG_PROC_FS
552 * Display some core information through /proc/cpuinfo.
556 c_show(struct seq_file *f, void *slot)
558 /* high-level stuff */
559 seq_printf(f, "CPU count\t: %u\n"
560 "CPU list\t: %*pbl\n"
561 "vendor_id\t: Tensilica\n"
562 "model\t\t: Xtensa " XCHAL_HW_VERSION_NAME "\n"
563 "core ID\t\t: " XCHAL_CORE_ID "\n"
565 "config ID\t: %08x:%08x\n"
567 "cpu MHz\t\t: %lu.%02lu\n"
568 "bogomips\t: %lu.%02lu\n",
570 cpumask_pr_args(cpu_online_mask),
571 XCHAL_BUILD_UNIQUE_ID,
572 xtensa_get_sr(SREG_EPC), xtensa_get_sr(SREG_EXCSAVE),
573 XCHAL_HAVE_BE ? "big" : "little",
575 (ccount_freq/10000) % 100,
576 loops_per_jiffy/(500000/HZ),
577 (loops_per_jiffy/(5000/HZ)) % 100);
578 seq_puts(f, "flags\t\t: "
590 #if XCHAL_NUM_PERF_COUNTERS
594 #if XCHAL_HAVE_DENSITY
597 #if XCHAL_HAVE_BOOLEANS
606 #if XCHAL_HAVE_MINMAX
612 #if XCHAL_HAVE_CLAMPS
624 #if XCHAL_HAVE_MUL32_HIGH
630 #if XCHAL_HAVE_S32C1I
633 #if XCHAL_HAVE_EXCLUSIVE
639 seq_printf(f,"physical aregs\t: %d\n"
643 "perf counters\t: %d\n",
648 XCHAL_NUM_PERF_COUNTERS);
652 seq_printf(f,"num ints\t: %d\n"
656 "debug level\t: %d\n",
657 XCHAL_NUM_INTERRUPTS,
658 XCHAL_NUM_EXTINTERRUPTS,
664 seq_printf(f,"icache line size: %d\n"
665 "icache ways\t: %d\n"
666 "icache size\t: %d\n"
668 #if XCHAL_ICACHE_LINE_LOCKABLE
672 "dcache line size: %d\n"
673 "dcache ways\t: %d\n"
674 "dcache size\t: %d\n"
676 #if XCHAL_DCACHE_IS_WRITEBACK
679 #if XCHAL_DCACHE_LINE_LOCKABLE
683 XCHAL_ICACHE_LINESIZE,
686 XCHAL_DCACHE_LINESIZE,
694 * We show only CPU #0 info.
697 c_start(struct seq_file *f, loff_t *pos)
699 return (*pos == 0) ? (void *)1 : NULL;
703 c_next(struct seq_file *f, void *v, loff_t *pos)
706 return c_start(f, pos);
710 c_stop(struct seq_file *f, void *v)
714 const struct seq_operations cpuinfo_op =
722 #endif /* CONFIG_PROC_FS */