2 * arch/xtensa/kernel/setup.c
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file "COPYING" in the main directory of this archive
8 * Copyright (C) 1995 Linus Torvalds
9 * Copyright (C) 2001 - 2005 Tensilica Inc.
10 * Copyright (C) 2014 - 2016 Cadence Design Systems Inc.
12 * Chris Zankel <chris@zankel.net>
13 * Joe Taylor <joe@tensilica.com, joetylr@yahoo.com>
15 * Marc Gauthier<marc@tensilica.com> <marc@alumni.uwaterloo.ca>
18 #include <linux/errno.h>
19 #include <linux/init.h>
21 #include <linux/proc_fs.h>
22 #include <linux/screen_info.h>
23 #include <linux/bootmem.h>
24 #include <linux/kernel.h>
25 #include <linux/percpu.h>
26 #include <linux/cpu.h>
28 #include <linux/of_fdt.h>
30 #if defined(CONFIG_VGA_CONSOLE) || defined(CONFIG_DUMMY_CONSOLE)
31 # include <linux/console.h>
35 # include <linux/seq_file.h>
38 #include <asm/bootparam.h>
39 #include <asm/mmu_context.h>
40 #include <asm/pgtable.h>
41 #include <asm/processor.h>
42 #include <asm/timex.h>
43 #include <asm/platform.h>
45 #include <asm/setup.h>
46 #include <asm/param.h>
48 #include <asm/sysmem.h>
50 #include <platform/hardware.h>
52 #if defined(CONFIG_VGA_CONSOLE) || defined(CONFIG_DUMMY_CONSOLE)
53 struct screen_info screen_info = {
56 .orig_video_cols = 80,
57 .orig_video_lines = 24,
58 .orig_video_isVGA = 1,
59 .orig_video_points = 16,
63 #ifdef CONFIG_BLK_DEV_INITRD
64 extern unsigned long initrd_start;
65 extern unsigned long initrd_end;
66 int initrd_is_mapped = 0;
67 extern int initrd_below_start_ok;
71 void *dtb_start = __dtb_start;
74 extern unsigned long loops_per_jiffy;
76 /* Command line specified as configuration option. */
78 static char __initdata command_line[COMMAND_LINE_SIZE];
80 #ifdef CONFIG_CMDLINE_BOOL
81 static char default_command_line[COMMAND_LINE_SIZE] __initdata = CONFIG_CMDLINE;
85 * Boot parameter parsing.
87 * The Xtensa port uses a list of variable-sized tags to pass data to
88 * the kernel. The first tag must be a BP_TAG_FIRST tag for the list
89 * to be recognised. The list is terminated with a zero-sized
93 typedef struct tagtable {
95 int (*parse)(const bp_tag_t*);
98 #define __tagtable(tag, fn) static tagtable_t __tagtable_##fn \
99 __attribute__((used, section(".taglist"))) = { tag, fn }
101 /* parse current tag */
103 static int __init parse_tag_mem(const bp_tag_t *tag)
105 struct bp_meminfo *mi = (struct bp_meminfo *)(tag->data);
107 if (mi->type != MEMORY_TYPE_CONVENTIONAL)
110 return memblock_add(mi->start, mi->end - mi->start);
113 __tagtable(BP_TAG_MEMORY, parse_tag_mem);
115 #ifdef CONFIG_BLK_DEV_INITRD
117 static int __init parse_tag_initrd(const bp_tag_t* tag)
119 struct bp_meminfo *mi = (struct bp_meminfo *)(tag->data);
121 initrd_start = (unsigned long)__va(mi->start);
122 initrd_end = (unsigned long)__va(mi->end);
127 __tagtable(BP_TAG_INITRD, parse_tag_initrd);
129 #endif /* CONFIG_BLK_DEV_INITRD */
133 static int __init parse_tag_fdt(const bp_tag_t *tag)
135 dtb_start = __va(tag->data[0]);
139 __tagtable(BP_TAG_FDT, parse_tag_fdt);
141 #endif /* CONFIG_OF */
143 static int __init parse_tag_cmdline(const bp_tag_t* tag)
145 strlcpy(command_line, (char *)(tag->data), COMMAND_LINE_SIZE);
149 __tagtable(BP_TAG_COMMAND_LINE, parse_tag_cmdline);
151 static int __init parse_bootparam(const bp_tag_t* tag)
153 extern tagtable_t __tagtable_begin, __tagtable_end;
156 /* Boot parameters must start with a BP_TAG_FIRST tag. */
158 if (tag->id != BP_TAG_FIRST) {
159 printk(KERN_WARNING "Invalid boot parameters!\n");
163 tag = (bp_tag_t*)((unsigned long)tag + sizeof(bp_tag_t) + tag->size);
165 /* Parse all tags. */
167 while (tag != NULL && tag->id != BP_TAG_LAST) {
168 for (t = &__tagtable_begin; t < &__tagtable_end; t++) {
169 if (tag->id == t->tag) {
174 if (t == &__tagtable_end)
175 printk(KERN_WARNING "Ignoring tag "
176 "0x%08x\n", tag->id);
177 tag = (bp_tag_t*)((unsigned long)(tag + 1) + tag->size);
185 #if !XCHAL_HAVE_PTP_MMU || XCHAL_HAVE_SPANNING_WAY
186 unsigned long xtensa_kio_paddr = XCHAL_KIO_DEFAULT_PADDR;
187 EXPORT_SYMBOL(xtensa_kio_paddr);
189 static int __init xtensa_dt_io_area(unsigned long node, const char *uname,
190 int depth, void *data)
192 const __be32 *ranges;
198 if (!of_flat_dt_is_compatible(node, "simple-bus"))
201 ranges = of_get_flat_dt_prop(node, "ranges", &len);
207 xtensa_kio_paddr = of_read_ulong(ranges+1, 1);
208 /* round down to nearest 256MB boundary */
209 xtensa_kio_paddr &= 0xf0000000;
214 static int __init xtensa_dt_io_area(unsigned long node, const char *uname,
215 int depth, void *data)
221 void __init early_init_dt_add_memory_arch(u64 base, u64 size)
224 memblock_add(base, size);
227 void * __init early_init_dt_alloc_memory_arch(u64 size, u64 align)
229 return __alloc_bootmem(size, align, 0);
232 void __init early_init_devtree(void *params)
234 early_init_dt_scan(params);
235 of_scan_flat_dt(xtensa_dt_io_area, NULL);
237 if (!command_line[0])
238 strlcpy(command_line, boot_command_line, COMMAND_LINE_SIZE);
241 #endif /* CONFIG_OF */
244 * Initialize architecture. (Early stage)
247 void __init init_arch(bp_tag_t *bp_start)
249 /* Parse boot parameters */
252 parse_bootparam(bp_start);
255 early_init_devtree(dtb_start);
258 #ifdef CONFIG_CMDLINE_BOOL
259 if (!command_line[0])
260 strlcpy(command_line, default_command_line, COMMAND_LINE_SIZE);
263 /* Early hook for platforms */
265 platform_init(bp_start);
267 /* Initialize MMU. */
273 * Initialize system. Setup memory and reserve regions.
277 extern char _stext[];
278 extern char _WindowVectors_text_start;
279 extern char _WindowVectors_text_end;
280 extern char _DebugInterruptVector_literal_start;
281 extern char _DebugInterruptVector_text_end;
282 extern char _KernelExceptionVector_literal_start;
283 extern char _KernelExceptionVector_text_end;
284 extern char _UserExceptionVector_literal_start;
285 extern char _UserExceptionVector_text_end;
286 extern char _DoubleExceptionVector_literal_start;
287 extern char _DoubleExceptionVector_text_end;
288 #if XCHAL_EXCM_LEVEL >= 2
289 extern char _Level2InterruptVector_text_start;
290 extern char _Level2InterruptVector_text_end;
292 #if XCHAL_EXCM_LEVEL >= 3
293 extern char _Level3InterruptVector_text_start;
294 extern char _Level3InterruptVector_text_end;
296 #if XCHAL_EXCM_LEVEL >= 4
297 extern char _Level4InterruptVector_text_start;
298 extern char _Level4InterruptVector_text_end;
300 #if XCHAL_EXCM_LEVEL >= 5
301 extern char _Level5InterruptVector_text_start;
302 extern char _Level5InterruptVector_text_end;
304 #if XCHAL_EXCM_LEVEL >= 6
305 extern char _Level6InterruptVector_text_start;
306 extern char _Level6InterruptVector_text_end;
309 extern char _SecondaryResetVector_text_start;
310 extern char _SecondaryResetVector_text_end;
313 static inline int __init_memblock mem_reserve(unsigned long start,
316 return memblock_reserve(start, end - start);
319 void __init setup_arch(char **cmdline_p)
321 *cmdline_p = command_line;
322 platform_setup(cmdline_p);
323 strlcpy(boot_command_line, *cmdline_p, COMMAND_LINE_SIZE);
325 /* Reserve some memory regions */
327 #ifdef CONFIG_BLK_DEV_INITRD
328 if (initrd_start < initrd_end) {
329 initrd_is_mapped = mem_reserve(__pa(initrd_start),
330 __pa(initrd_end)) == 0;
331 initrd_below_start_ok = 1;
337 mem_reserve(__pa(_stext), __pa(_end));
339 #ifdef CONFIG_VECTORS_OFFSET
340 mem_reserve(__pa(&_WindowVectors_text_start),
341 __pa(&_WindowVectors_text_end));
343 mem_reserve(__pa(&_DebugInterruptVector_literal_start),
344 __pa(&_DebugInterruptVector_text_end));
346 mem_reserve(__pa(&_KernelExceptionVector_literal_start),
347 __pa(&_KernelExceptionVector_text_end));
349 mem_reserve(__pa(&_UserExceptionVector_literal_start),
350 __pa(&_UserExceptionVector_text_end));
352 mem_reserve(__pa(&_DoubleExceptionVector_literal_start),
353 __pa(&_DoubleExceptionVector_text_end));
355 #if XCHAL_EXCM_LEVEL >= 2
356 mem_reserve(__pa(&_Level2InterruptVector_text_start),
357 __pa(&_Level2InterruptVector_text_end));
359 #if XCHAL_EXCM_LEVEL >= 3
360 mem_reserve(__pa(&_Level3InterruptVector_text_start),
361 __pa(&_Level3InterruptVector_text_end));
363 #if XCHAL_EXCM_LEVEL >= 4
364 mem_reserve(__pa(&_Level4InterruptVector_text_start),
365 __pa(&_Level4InterruptVector_text_end));
367 #if XCHAL_EXCM_LEVEL >= 5
368 mem_reserve(__pa(&_Level5InterruptVector_text_start),
369 __pa(&_Level5InterruptVector_text_end));
371 #if XCHAL_EXCM_LEVEL >= 6
372 mem_reserve(__pa(&_Level6InterruptVector_text_start),
373 __pa(&_Level6InterruptVector_text_end));
376 #endif /* CONFIG_VECTORS_OFFSET */
379 mem_reserve(__pa(&_SecondaryResetVector_text_start),
380 __pa(&_SecondaryResetVector_text_end));
385 unflatten_and_copy_device_tree();
395 # if defined(CONFIG_VGA_CONSOLE)
396 conswitchp = &vga_con;
397 # elif defined(CONFIG_DUMMY_CONSOLE)
398 conswitchp = &dummy_con;
403 platform_pcibios_init();
407 static DEFINE_PER_CPU(struct cpu, cpu_data);
409 static int __init topology_init(void)
413 for_each_possible_cpu(i) {
414 struct cpu *cpu = &per_cpu(cpu_data, i);
415 cpu->hotpluggable = !!i;
416 register_cpu(cpu, i);
421 subsys_initcall(topology_init);
425 #if XCHAL_HAVE_PTP_MMU && IS_ENABLED(CONFIG_MMU)
428 * We have full MMU: all autoload ways, ways 7, 8 and 9 of DTLB must
430 * Way 4 is not currently used by linux.
431 * Ways 5 and 6 shall not be touched on MMUv2 as they are hardwired.
432 * Way 5 shall be flushed and way 6 shall be set to identity mapping
435 local_flush_tlb_all();
436 invalidate_page_directory();
437 #if XCHAL_HAVE_SPANNING_WAY
440 unsigned long vaddr = (unsigned long)cpu_reset;
441 unsigned long paddr = __pa(vaddr);
442 unsigned long tmpaddr = vaddr + SZ_512M;
443 unsigned long tmp0, tmp1, tmp2, tmp3;
446 * Find a place for the temporary mapping. It must not be
447 * in the same 512MB region with vaddr or paddr, otherwise
448 * there may be multihit exception either on entry to the
449 * temporary mapping, or on entry to the identity mapping.
450 * (512MB is the biggest page size supported by TLB.)
452 while (((tmpaddr ^ paddr) & -SZ_512M) == 0)
455 /* Invalidate mapping in the selected temporary area */
456 if (itlb_probe(tmpaddr) & BIT(ITLB_HIT_BIT))
457 invalidate_itlb_entry(itlb_probe(tmpaddr));
458 if (itlb_probe(tmpaddr + PAGE_SIZE) & BIT(ITLB_HIT_BIT))
459 invalidate_itlb_entry(itlb_probe(tmpaddr + PAGE_SIZE));
462 * Map two consecutive pages starting at the physical address
463 * of this function to the temporary mapping area.
465 write_itlb_entry(__pte((paddr & PAGE_MASK) |
469 tmpaddr & PAGE_MASK);
470 write_itlb_entry(__pte(((paddr & PAGE_MASK) + PAGE_SIZE) |
474 (tmpaddr & PAGE_MASK) + PAGE_SIZE);
476 /* Reinitialize TLB */
477 __asm__ __volatile__ ("movi %0, 1f\n\t"
483 * No literal, data or stack access
487 /* Initialize *tlbcfg */
489 "wsr %0, itlbcfg\n\t"
490 "wsr %0, dtlbcfg\n\t"
491 /* Invalidate TLB way 5 */
498 "addi %0, %0, -1\n\t"
500 /* Initialize TLB way 6 */
509 "addi %0, %0, -1\n\t"
512 /* Jump to identity mapping */
515 /* Complete way 6 initialization */
518 /* Invalidate temporary mapping */
523 : "=&a"(tmp0), "=&a"(tmp1), "=&a"(tmp2),
525 : "a"(tmpaddr - vaddr),
527 "a"(SZ_128M), "a"(SZ_512M),
529 "a"((tmpaddr + SZ_512M) & PAGE_MASK)
534 __asm__ __volatile__ ("movi a2, 0\n\t"
535 "wsr a2, icountlevel\n\t"
538 #if XCHAL_NUM_IBREAK > 0
539 "wsr a2, ibreakenable\n\t"
549 : "a" (XCHAL_RESET_VECTOR_VADDR)
555 void machine_restart(char * cmd)
560 void machine_halt(void)
566 void machine_power_off(void)
568 platform_power_off();
571 #ifdef CONFIG_PROC_FS
574 * Display some core information through /proc/cpuinfo.
578 c_show(struct seq_file *f, void *slot)
580 /* high-level stuff */
581 seq_printf(f, "CPU count\t: %u\n"
582 "CPU list\t: %*pbl\n"
583 "vendor_id\t: Tensilica\n"
584 "model\t\t: Xtensa " XCHAL_HW_VERSION_NAME "\n"
585 "core ID\t\t: " XCHAL_CORE_ID "\n"
588 "cpu MHz\t\t: %lu.%02lu\n"
589 "bogomips\t: %lu.%02lu\n",
591 cpumask_pr_args(cpu_online_mask),
592 XCHAL_BUILD_UNIQUE_ID,
593 XCHAL_HAVE_BE ? "big" : "little",
595 (ccount_freq/10000) % 100,
596 loops_per_jiffy/(500000/HZ),
597 (loops_per_jiffy/(5000/HZ)) % 100);
598 seq_puts(f, "flags\t\t: "
608 #if XCHAL_HAVE_DENSITY
611 #if XCHAL_HAVE_BOOLEANS
620 #if XCHAL_HAVE_MINMAX
626 #if XCHAL_HAVE_CLAMPS
638 #if XCHAL_HAVE_MUL32_HIGH
644 #if XCHAL_HAVE_S32C1I
650 seq_printf(f,"physical aregs\t: %d\n"
661 seq_printf(f,"num ints\t: %d\n"
665 "debug level\t: %d\n",
666 XCHAL_NUM_INTERRUPTS,
667 XCHAL_NUM_EXTINTERRUPTS,
673 seq_printf(f,"icache line size: %d\n"
674 "icache ways\t: %d\n"
675 "icache size\t: %d\n"
677 #if XCHAL_ICACHE_LINE_LOCKABLE
681 "dcache line size: %d\n"
682 "dcache ways\t: %d\n"
683 "dcache size\t: %d\n"
685 #if XCHAL_DCACHE_IS_WRITEBACK
688 #if XCHAL_DCACHE_LINE_LOCKABLE
692 XCHAL_ICACHE_LINESIZE,
695 XCHAL_DCACHE_LINESIZE,
703 * We show only CPU #0 info.
706 c_start(struct seq_file *f, loff_t *pos)
708 return (*pos == 0) ? (void *)1 : NULL;
712 c_next(struct seq_file *f, void *v, loff_t *pos)
715 return c_start(f, pos);
719 c_stop(struct seq_file *f, void *v)
723 const struct seq_operations cpuinfo_op =
731 #endif /* CONFIG_PROC_FS */