2 * Xtensa hardware breakpoints/watchpoints handling functions
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file "COPYING" in the main directory of this archive
8 * Copyright (C) 2016 Cadence Design Systems Inc.
11 #include <linux/hw_breakpoint.h>
12 #include <linux/log2.h>
13 #include <linux/percpu.h>
14 #include <linux/perf_event.h>
16 #include <asm/hw_breakpoint.h>
18 /* Breakpoint currently in use for each IBREAKA. */
19 static DEFINE_PER_CPU(struct perf_event *, bp_on_reg[XCHAL_NUM_IBREAK]);
21 /* Watchpoint currently in use for each DBREAKA. */
22 static DEFINE_PER_CPU(struct perf_event *, wp_on_reg[XCHAL_NUM_DBREAK]);
24 int hw_breakpoint_slots(int type)
28 return XCHAL_NUM_IBREAK;
30 return XCHAL_NUM_DBREAK;
32 pr_warn("unknown slot type: %d\n", type);
37 int arch_check_bp_in_kernelspace(struct arch_hw_breakpoint *hw)
45 return (va >= TASK_SIZE) && ((va + len - 1) >= TASK_SIZE);
49 * Construct an arch_hw_breakpoint from a perf_event.
51 int hw_breakpoint_arch_parse(struct perf_event *bp,
52 const struct perf_event_attr *attr,
53 struct arch_hw_breakpoint *hw)
56 switch (attr->bp_type) {
58 hw->type = XTENSA_BREAKPOINT_EXECUTE;
61 hw->type = XTENSA_BREAKPOINT_LOAD;
64 hw->type = XTENSA_BREAKPOINT_STORE;
66 case HW_BREAKPOINT_RW:
67 hw->type = XTENSA_BREAKPOINT_LOAD | XTENSA_BREAKPOINT_STORE;
74 hw->len = attr->bp_len;
75 if (hw->len < 1 || hw->len > 64 || !is_power_of_2(hw->len))
79 hw->address = attr->bp_addr;
80 if (hw->address & (hw->len - 1))
86 int hw_breakpoint_exceptions_notify(struct notifier_block *unused,
87 unsigned long val, void *data)
92 static void xtensa_wsr(unsigned long v, u8 sr)
94 /* We don't have indexed wsr and creating instruction dynamically
95 * doesn't seem worth it given how small XCHAL_NUM_IBREAK and
96 * XCHAL_NUM_DBREAK are. Thus the switch. In case build breaks here
97 * the switch below needs to be extended.
99 BUILD_BUG_ON(XCHAL_NUM_IBREAK > 2);
100 BUILD_BUG_ON(XCHAL_NUM_DBREAK > 2);
103 #if XCHAL_NUM_IBREAK > 0
104 case SREG_IBREAKA + 0:
105 xtensa_set_sr(v, SREG_IBREAKA + 0);
108 #if XCHAL_NUM_IBREAK > 1
109 case SREG_IBREAKA + 1:
110 xtensa_set_sr(v, SREG_IBREAKA + 1);
114 #if XCHAL_NUM_DBREAK > 0
115 case SREG_DBREAKA + 0:
116 xtensa_set_sr(v, SREG_DBREAKA + 0);
118 case SREG_DBREAKC + 0:
119 xtensa_set_sr(v, SREG_DBREAKC + 0);
122 #if XCHAL_NUM_DBREAK > 1
123 case SREG_DBREAKA + 1:
124 xtensa_set_sr(v, SREG_DBREAKA + 1);
127 case SREG_DBREAKC + 1:
128 xtensa_set_sr(v, SREG_DBREAKC + 1);
134 static int alloc_slot(struct perf_event **slot, size_t n,
135 struct perf_event *bp)
139 for (i = 0; i < n; ++i) {
148 static void set_ibreak_regs(int reg, struct perf_event *bp)
150 struct arch_hw_breakpoint *info = counter_arch_bp(bp);
151 unsigned long ibreakenable;
153 xtensa_wsr(info->address, SREG_IBREAKA + reg);
154 ibreakenable = xtensa_get_sr(SREG_IBREAKENABLE);
155 xtensa_set_sr(ibreakenable | (1 << reg), SREG_IBREAKENABLE);
158 static void set_dbreak_regs(int reg, struct perf_event *bp)
160 struct arch_hw_breakpoint *info = counter_arch_bp(bp);
161 unsigned long dbreakc = DBREAKC_MASK_MASK & -info->len;
163 if (info->type & XTENSA_BREAKPOINT_LOAD)
164 dbreakc |= DBREAKC_LOAD_MASK;
165 if (info->type & XTENSA_BREAKPOINT_STORE)
166 dbreakc |= DBREAKC_STOR_MASK;
168 xtensa_wsr(info->address, SREG_DBREAKA + reg);
169 xtensa_wsr(dbreakc, SREG_DBREAKC + reg);
172 int arch_install_hw_breakpoint(struct perf_event *bp)
176 if (counter_arch_bp(bp)->type == XTENSA_BREAKPOINT_EXECUTE) {
178 i = alloc_slot(this_cpu_ptr(bp_on_reg), XCHAL_NUM_IBREAK, bp);
181 set_ibreak_regs(i, bp);
185 i = alloc_slot(this_cpu_ptr(wp_on_reg), XCHAL_NUM_DBREAK, bp);
188 set_dbreak_regs(i, bp);
193 static int free_slot(struct perf_event **slot, size_t n,
194 struct perf_event *bp)
198 for (i = 0; i < n; ++i) {
207 void arch_uninstall_hw_breakpoint(struct perf_event *bp)
209 struct arch_hw_breakpoint *info = counter_arch_bp(bp);
212 if (info->type == XTENSA_BREAKPOINT_EXECUTE) {
213 unsigned long ibreakenable;
216 i = free_slot(this_cpu_ptr(bp_on_reg), XCHAL_NUM_IBREAK, bp);
218 ibreakenable = xtensa_get_sr(SREG_IBREAKENABLE);
219 xtensa_set_sr(ibreakenable & ~(1 << i),
224 i = free_slot(this_cpu_ptr(wp_on_reg), XCHAL_NUM_DBREAK, bp);
226 xtensa_wsr(0, SREG_DBREAKC + i);
230 void hw_breakpoint_pmu_read(struct perf_event *bp)
234 void flush_ptrace_hw_breakpoint(struct task_struct *tsk)
237 struct thread_struct *t = &tsk->thread;
239 for (i = 0; i < XCHAL_NUM_IBREAK; ++i) {
240 if (t->ptrace_bp[i]) {
241 unregister_hw_breakpoint(t->ptrace_bp[i]);
242 t->ptrace_bp[i] = NULL;
245 for (i = 0; i < XCHAL_NUM_DBREAK; ++i) {
246 if (t->ptrace_wp[i]) {
247 unregister_hw_breakpoint(t->ptrace_wp[i]);
248 t->ptrace_wp[i] = NULL;
254 * Set ptrace breakpoint pointers to zero for this task.
255 * This is required in order to prevent child processes from unregistering
256 * breakpoints held by their parent.
258 void clear_ptrace_hw_breakpoint(struct task_struct *tsk)
260 memset(tsk->thread.ptrace_bp, 0, sizeof(tsk->thread.ptrace_bp));
261 memset(tsk->thread.ptrace_wp, 0, sizeof(tsk->thread.ptrace_wp));
264 void restore_dbreak(void)
268 for (i = 0; i < XCHAL_NUM_DBREAK; ++i) {
269 struct perf_event *bp = this_cpu_ptr(wp_on_reg)[i];
272 set_dbreak_regs(i, bp);
274 clear_thread_flag(TIF_DB_DISABLED);
277 int check_hw_breakpoint(struct pt_regs *regs)
279 if (regs->debugcause & BIT(DEBUGCAUSE_IBREAK_BIT)) {
281 struct perf_event **bp = this_cpu_ptr(bp_on_reg);
283 for (i = 0; i < XCHAL_NUM_IBREAK; ++i) {
284 if (bp[i] && !bp[i]->attr.disabled &&
285 regs->pc == bp[i]->attr.bp_addr)
286 perf_bp_event(bp[i], regs);
289 } else if (regs->debugcause & BIT(DEBUGCAUSE_DBREAK_BIT)) {
290 struct perf_event **bp = this_cpu_ptr(wp_on_reg);
291 int dbnum = (regs->debugcause & DEBUGCAUSE_DBNUM_MASK) >>
292 DEBUGCAUSE_DBNUM_SHIFT;
294 if (dbnum < XCHAL_NUM_DBREAK && bp[dbnum]) {
295 if (user_mode(regs)) {
296 perf_bp_event(bp[dbnum], regs);
298 set_thread_flag(TIF_DB_DISABLED);
299 xtensa_wsr(0, SREG_DBREAKC + dbnum);
303 "Wrong/unconfigured DBNUM reported in DEBUGCAUSE: %d\n",