2 * Low-level exception handling
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file "COPYING" in the main directory of this archive
8 * Copyright (C) 2004 - 2008 by Tensilica Inc.
9 * Copyright (C) 2015 Cadence Design Systems Inc.
11 * Chris Zankel <chris@zankel.net>
15 #include <linux/linkage.h>
16 #include <linux/pgtable.h>
17 #include <asm/asm-offsets.h>
18 #include <asm/asmmacro.h>
19 #include <asm/processor.h>
20 #include <asm/coprocessor.h>
21 #include <asm/thread_info.h>
22 #include <asm/asm-uaccess.h>
23 #include <asm/unistd.h>
24 #include <asm/ptrace.h>
25 #include <asm/current.h>
27 #include <asm/signal.h>
28 #include <asm/tlbflush.h>
29 #include <variant/tie-asm.h>
31 /* Unimplemented features. */
33 #undef KERNEL_STACK_OVERFLOW_CHECK
41 * Macro to find first bit set in WINDOWBASE from the left + 1
48 .macro ffs_ws bit mask
51 nsau \bit, \mask # 32-WSBITS ... 31 (32 iff 0)
52 addi \bit, \bit, WSBITS - 32 + 1 # uppest bit set -> return 1
56 _bltui \mask, 0x10000, 99f
58 extui \mask, \mask, 16, 16
61 99: _bltui \mask, 0x100, 99f
65 99: _bltui \mask, 0x10, 99f
68 99: _bltui \mask, 0x4, 99f
71 99: _bltui \mask, 0x2, 99f
79 .macro irq_save flags tmp
81 #if defined(CONFIG_DEBUG_KERNEL) && (LOCKLEVEL | TOPLEVEL) >= XCHAL_DEBUGLEVEL
83 extui \tmp, \flags, PS_INTLEVEL_SHIFT, PS_INTLEVEL_WIDTH
84 bgei \tmp, LOCKLEVEL, 99f
90 or \flags, \flags, \tmp
95 rsil \flags, LOCKLEVEL
99 /* ----------------- DEFAULT FIRST LEVEL EXCEPTION HANDLERS ----------------- */
102 * First-level exception handler for user exceptions.
103 * Save some special registers, extra states and all registers in the AR
104 * register file that were in use in the user task, and jump to the common
106 * We save SAR (used to calculate WMASK), and WB and WS (we don't have to
107 * save them for kernel exceptions).
109 * Entry condition for user_exception:
111 * a0: trashed, original value saved on stack (PT_AREG0)
113 * a2: new stack pointer, original value in depc
115 * depc: a2, original value saved on stack (PT_DEPC)
116 * excsave1: dispatch table
118 * PT_DEPC >= VALID_DOUBLE_EXCEPTION_ADDRESS: double exception, DEPC
119 * < VALID_DOUBLE_EXCEPTION_ADDRESS: regular exception
121 * Entry condition for _user_exception:
123 * a0-a3 and depc have been saved to PT_AREG0...PT_AREG3 and PT_DEPC
124 * excsave has been restored, and
125 * stack pointer (a1) has been set.
127 * Note: _user_exception might be at an odd address. Don't use call0..call12
131 ENTRY(user_exception)
133 /* Save a1, a2, a3, and set SP. */
136 s32i a1, a2, PT_AREG1
137 s32i a0, a2, PT_AREG2
138 s32i a3, a2, PT_AREG3
141 .globl _user_exception
144 /* Save SAR and turn off single stepping */
147 wsr a2, depc # terminate user stack trace with 0
151 s32i a2, a1, PT_ICOUNTLEVEL
153 #if XCHAL_HAVE_THREADPTR
155 s32i a2, a1, PT_THREADPTR
158 /* Rotate ws so that the current windowbase is at bit0. */
159 /* Assume ws = xxwww1yyyy. Rotate ws right, so that a2 = yyyyxxwww1 */
164 s32i a2, a1, PT_WINDOWBASE
165 s32i a3, a1, PT_WINDOWSTART
166 slli a2, a3, 32-WSBITS
168 srli a2, a2, 32-WSBITS
169 s32i a2, a1, PT_WMASK # needed for restoring registers
171 /* Save only live registers. */
174 s32i a4, a1, PT_AREG4
175 s32i a5, a1, PT_AREG5
176 s32i a6, a1, PT_AREG6
177 s32i a7, a1, PT_AREG7
179 s32i a8, a1, PT_AREG8
180 s32i a9, a1, PT_AREG9
181 s32i a10, a1, PT_AREG10
182 s32i a11, a1, PT_AREG11
184 s32i a12, a1, PT_AREG12
185 s32i a13, a1, PT_AREG13
186 s32i a14, a1, PT_AREG14
187 s32i a15, a1, PT_AREG15
188 _bnei a2, 1, 1f # only one valid frame?
190 /* Only one valid frame, skip saving regs. */
194 /* Save the remaining registers.
195 * We have to save all registers up to the first '1' from
196 * the right, except the current frame (bit 0).
197 * Assume a2 is: 001001000110001
198 * All register frames starting from the top field to the marked '1'
202 1: addi a3, a2, -1 # eliminate '1' in bit 0: yyyyxxww0
203 neg a3, a3 # yyyyxxww0 -> YYYYXXWW1+1
204 and a3, a3, a2 # max. only one bit is set
206 /* Find number of frames to save */
208 ffs_ws a0, a3 # number of frames to the '1' from left
210 /* Store information into WMASK:
211 * bits 0..3: xxx1 masked lower 4 bits of the rotated windowstart,
212 * bits 4...: number of valid 4-register frames
215 slli a3, a0, 4 # number of frames to save in bits 8..4
216 extui a2, a2, 0, 4 # mask for the first 16 registers
218 s32i a2, a1, PT_WMASK # needed when we restore the reg-file
220 /* Save 4 registers at a time */
223 s32i a0, a5, PT_AREG_END - 16
224 s32i a1, a5, PT_AREG_END - 12
225 s32i a2, a5, PT_AREG_END - 8
226 s32i a3, a5, PT_AREG_END - 4
231 /* WINDOWBASE still in SAR! */
233 rsr a2, sar # original WINDOWBASE
237 wsr a3, windowstart # set corresponding WINDOWSTART bit
238 wsr a2, windowbase # and WINDOWSTART
241 /* We are back to the original stack pointer (a1) */
243 2: /* Now, jump to the common exception handler. */
247 ENDPROC(user_exception)
250 * First-level exit handler for kernel exceptions
251 * Save special registers and the live window frame.
252 * Note: Even though we changes the stack pointer, we don't have to do a
253 * MOVSP here, as we do that when we return from the exception.
254 * (See comment in the kernel exception exit code)
256 * Entry condition for kernel_exception:
258 * a0: trashed, original value saved on stack (PT_AREG0)
260 * a2: new stack pointer, original in DEPC
262 * depc: a2, original value saved on stack (PT_DEPC)
263 * excsave_1: dispatch table
265 * PT_DEPC >= VALID_DOUBLE_EXCEPTION_ADDRESS: double exception, DEPC
266 * < VALID_DOUBLE_EXCEPTION_ADDRESS: regular exception
268 * Entry condition for _kernel_exception:
270 * a0-a3 and depc have been saved to PT_AREG0...PT_AREG3 and PT_DEPC
271 * excsave has been restored, and
272 * stack pointer (a1) has been set.
274 * Note: _kernel_exception might be at an odd address. Don't use call0..call12
277 ENTRY(kernel_exception)
279 /* Save a1, a2, a3, and set SP. */
281 rsr a0, depc # get a2
282 s32i a1, a2, PT_AREG1
283 s32i a0, a2, PT_AREG2
284 s32i a3, a2, PT_AREG3
287 .globl _kernel_exception
290 /* Save SAR and turn off single stepping */
296 s32i a2, a1, PT_ICOUNTLEVEL
298 /* Rotate ws so that the current windowbase is at bit0. */
299 /* Assume ws = xxwww1yyyy. Rotate ws right, so that a2 = yyyyxxwww1 */
301 rsr a2, windowbase # don't need to save these, we only
302 rsr a3, windowstart # need shifted windowstart: windowmask
304 slli a2, a3, 32-WSBITS
306 srli a2, a2, 32-WSBITS
307 s32i a2, a1, PT_WMASK # needed for kernel_exception_exit
309 /* Save only the live window-frame */
312 s32i a4, a1, PT_AREG4
313 s32i a5, a1, PT_AREG5
314 s32i a6, a1, PT_AREG6
315 s32i a7, a1, PT_AREG7
317 s32i a8, a1, PT_AREG8
318 s32i a9, a1, PT_AREG9
319 s32i a10, a1, PT_AREG10
320 s32i a11, a1, PT_AREG11
322 s32i a12, a1, PT_AREG12
323 s32i a13, a1, PT_AREG13
324 s32i a14, a1, PT_AREG14
325 s32i a15, a1, PT_AREG15
329 /* Copy spill slots of a0 and a1 to imitate movsp
330 * in order to keep exception stack continuous
333 l32i a0, a1, PT_SIZE + 4
337 l32i a0, a1, PT_AREG0 # restore saved a0
340 #ifdef KERNEL_STACK_OVERFLOW_CHECK
342 /* Stack overflow check, for debugging */
343 extui a2, a1, TASK_SIZE_BITS,XX
345 _bge a2, a3, out_of_stack_panic
350 * This is the common exception handler.
351 * We get here from the user exception handler or simply by falling through
352 * from the kernel exception handler.
353 * Save the remaining special registers, switch to kernel mode, and jump
354 * to the second-level exception handler.
360 /* Save some registers, disable loops and clear the syscall flag. */
364 s32i a2, a1, PT_DEBUGCAUSE
369 s32i a2, a1, PT_SYSCALL
371 s32i a3, a1, PT_EXCVADDR
374 s32i a2, a1, PT_LCOUNT
377 #if XCHAL_HAVE_EXCLUSIVE
378 /* Clear exclusive access monitor set by interrupted code */
382 /* It is now save to restore the EXC_TABLE_FIXUP variable. */
387 s32i a2, a1, PT_EXCCAUSE
388 s32i a3, a0, EXC_TABLE_FIXUP
390 /* All unrecoverable states are saved on stack, now, and a1 is valid.
391 * Now we can allow exceptions again. In case we've got an interrupt
392 * PS.INTLEVEL is set to LOCKLEVEL disabling furhter interrupts,
393 * otherwise it's left unchanged.
395 * Set PS(EXCM = 0, UM = 0, RING = 0, OWB = 0, WOE = 1, INTLEVEL = X)
399 s32i a3, a1, PT_PS # save ps
402 /* Correct PS needs to be saved in the PT_PS:
403 * - in case of exception or level-1 interrupt it's in the PS,
404 * and is already saved.
405 * - in case of medium level interrupt it's in the excsave2.
407 movi a0, EXCCAUSE_MAPPED_NMI
408 extui a3, a3, PS_INTLEVEL_SHIFT, PS_INTLEVEL_WIDTH
409 beq a2, a0, .Lmedium_level_irq
410 bnei a2, EXCCAUSE_LEVEL1_INTERRUPT, .Lexception
411 beqz a3, .Llevel1_irq # level-1 IRQ sets ps.intlevel to 0
415 s32i a0, a1, PT_PS # save medium-level interrupt ps
416 bgei a3, LOCKLEVEL, .Lexception
425 addi a2, a2, -EXCCAUSE_LEVEL1_INTERRUPT
427 extui a3, a3, PS_INTLEVEL_SHIFT, PS_INTLEVEL_WIDTH
429 moveqz a3, a0, a2 # a3 = LOCKLEVEL iff interrupt
435 /* restore return address (or 0 if return to userspace) */
438 rsync # PS.WOE => rsync => overflow
440 /* Save lbeg, lend */
450 #if XCHAL_HAVE_S32C1I
452 s32i a3, a1, PT_SCOMPARE1
455 /* Save optional registers. */
457 save_xtregs_opt a1 a3 a4 a5 a6 a7 PT_XTREGS_OPT
459 /* Go to second-level dispatcher. Set up parameters to pass to the
460 * exception handler and call the exception handler.
464 mov a6, a1 # pass stack frame
465 mov a7, a2 # pass EXCCAUSE
467 l32i a4, a4, EXC_TABLE_DEFAULT # load handler
469 /* Call the second-level handler */
473 /* Jump here for exception exit */
474 .global common_exception_return
475 common_exception_return:
478 l32i a2, a1, PT_EXCCAUSE
479 movi a3, EXCCAUSE_MAPPED_NMI
480 beq a2, a3, .LNMIexit
484 #ifdef CONFIG_TRACE_IRQFLAGS
485 call4 trace_hardirqs_off
488 /* Jump if we are returning from kernel exceptions. */
491 GET_THREAD_INFO(a2, a1)
492 l32i a4, a2, TI_FLAGS
493 _bbci.l a3, PS_UM_BIT, 6f
495 /* Specific to a user exception exit:
496 * We need to check some flags for signal handling and rescheduling,
497 * and have to restore WB and WS, extra states, and all registers
498 * in the register file that were in use in the user task.
499 * Note that we don't disable interrupts here.
502 _bbsi.l a4, TIF_NEED_RESCHED, 3f
503 movi a2, _TIF_SIGPENDING | _TIF_NOTIFY_RESUME | _TIF_NOTIFY_SIGNAL
506 2: l32i a4, a1, PT_DEPC
507 bgeui a4, VALID_DOUBLE_EXCEPTION_ADDRESS, 4f
509 /* Call do_signal() */
511 #ifdef CONFIG_TRACE_IRQFLAGS
512 call4 trace_hardirqs_on
516 call4 do_notify_resume # int do_notify_resume(struct pt_regs*)
521 #ifdef CONFIG_TRACE_IRQFLAGS
522 call4 trace_hardirqs_on
525 call4 schedule # void schedule (void)
528 #ifdef CONFIG_PREEMPTION
530 _bbci.l a4, TIF_NEED_RESCHED, 4f
532 /* Check current_thread_info->preempt_count */
534 l32i a4, a2, TI_PRE_COUNT
536 call4 preempt_schedule_irq
543 _bbci.l a3, PS_UM_BIT, 4f
547 #ifdef CONFIG_HAVE_HW_BREAKPOINT
548 _bbci.l a4, TIF_DB_DISABLED, 7f
552 #ifdef CONFIG_DEBUG_TLB_SANITY
554 bgeui a4, VALID_DOUBLE_EXCEPTION_ADDRESS, 4f
555 call4 check_tlb_sanity
559 #ifdef CONFIG_TRACE_IRQFLAGS
560 extui a4, a3, PS_INTLEVEL_SHIFT, PS_INTLEVEL_WIDTH
561 bgei a4, LOCKLEVEL, 1f
562 call4 trace_hardirqs_on
565 /* Restore optional registers. */
567 load_xtregs_opt a1 a2 a4 a5 a6 a7 PT_XTREGS_OPT
569 /* Restore SCOMPARE1 */
571 #if XCHAL_HAVE_S32C1I
572 l32i a2, a1, PT_SCOMPARE1
575 wsr a3, ps /* disable interrupts */
577 _bbci.l a3, PS_UM_BIT, kernel_exception_exit
581 /* Restore the state of the task and return from the exception. */
583 /* Switch to the user thread WINDOWBASE. Save SP temporarily in DEPC */
585 l32i a2, a1, PT_WINDOWBASE
586 l32i a3, a1, PT_WINDOWSTART
587 wsr a1, depc # use DEPC as temp storage
588 wsr a3, windowstart # restore WINDOWSTART
589 ssr a2 # preserve user's WB in the SAR
590 wsr a2, windowbase # switch to user's saved WB
592 rsr a1, depc # restore stack pointer
593 l32i a2, a1, PT_WMASK # register frames saved (in bits 4...9)
594 rotw -1 # we restore a4..a7
595 _bltui a6, 16, 1f # only have to restore current window?
597 /* The working registers are a0 and a3. We are restoring to
598 * a4..a7. Be careful not to destroy what we have just restored.
599 * Note: wmask has the format YYYYM:
600 * Y: number of registers saved in groups of 4
601 * M: 4 bit mask of first 16 registers
607 2: rotw -1 # a0..a3 become a4..a7
608 addi a3, a7, -4*4 # next iteration
609 addi a2, a6, -16 # decrementing Y in WMASK
610 l32i a4, a3, PT_AREG_END + 0
611 l32i a5, a3, PT_AREG_END + 4
612 l32i a6, a3, PT_AREG_END + 8
613 l32i a7, a3, PT_AREG_END + 12
616 /* Clear unrestored registers (don't leak anything to user-land */
618 1: rsr a0, windowbase
622 extui a3, a3, 0, WBBITS
632 /* We are back were we were when we started.
633 * Note: a2 still contains WMASK (if we've returned to the original
634 * frame where we had loaded a2), or at least the lower 4 bits
635 * (if we have restored WSBITS-1 frames).
639 #if XCHAL_HAVE_THREADPTR
640 l32i a3, a1, PT_THREADPTR
644 j common_exception_exit
646 /* This is the kernel exception exit.
647 * We avoided to do a MOVSP when we entered the exception, but we
648 * have to do it here.
651 kernel_exception_exit:
653 /* Check if we have to do a movsp.
655 * We only have to do a movsp if the previous window-frame has
656 * been spilled to the *temporary* exception stack instead of the
657 * task's stack. This is the case if the corresponding bit in
658 * WINDOWSTART for the previous window-frame was set before
659 * (not spilled) but is zero now (spilled).
660 * If this bit is zero, all other bits except the one for the
661 * current window frame are also zero. So, we can use a simple test:
662 * 'and' WINDOWSTART and WINDOWSTART-1:
664 * (XXXXXX1[0]* - 1) AND XXXXXX1[0]* = XXXXXX0[0]*
666 * The result is zero only if one bit was set.
668 * (Note: We might have gone through several task switches before
669 * we come back to the current task, so WINDOWBASE might be
670 * different from the time the exception occurred.)
673 /* Test WINDOWSTART before and after the exception.
674 * We actually have WMASK, so we only have to test if it is 1 or not.
677 l32i a2, a1, PT_WMASK
678 _beqi a2, 1, common_exception_exit # Spilled before exception,jump
680 /* Test WINDOWSTART now. If spilled, do the movsp */
685 _bnez a3, common_exception_exit
687 /* Do a movsp (we returned from a call4, so we have at least a0..a7) */
692 s32i a3, a1, PT_SIZE+0
693 s32i a4, a1, PT_SIZE+4
696 s32i a3, a1, PT_SIZE+8
697 s32i a4, a1, PT_SIZE+12
699 /* Common exception exit.
700 * We restore the special register and the current window frame, and
701 * return from the exception.
703 * Note: We expect a2 to hold PT_WMASK
706 common_exception_exit:
708 /* Restore address registers. */
711 l32i a4, a1, PT_AREG4
712 l32i a5, a1, PT_AREG5
713 l32i a6, a1, PT_AREG6
714 l32i a7, a1, PT_AREG7
716 l32i a8, a1, PT_AREG8
717 l32i a9, a1, PT_AREG9
718 l32i a10, a1, PT_AREG10
719 l32i a11, a1, PT_AREG11
721 l32i a12, a1, PT_AREG12
722 l32i a13, a1, PT_AREG13
723 l32i a14, a1, PT_AREG14
724 l32i a15, a1, PT_AREG15
726 /* Restore PC, SAR */
728 1: l32i a2, a1, PT_PC
733 /* Restore LBEG, LEND, LCOUNT */
738 l32i a2, a1, PT_LCOUNT
743 /* We control single stepping through the ICOUNTLEVEL register. */
745 l32i a2, a1, PT_ICOUNTLEVEL
750 /* Check if it was double exception. */
753 l32i a3, a1, PT_AREG3
754 l32i a2, a1, PT_AREG2
755 _bgeui a0, VALID_DOUBLE_EXCEPTION_ADDRESS, 1f
757 /* Restore a0...a3 and return */
759 l32i a0, a1, PT_AREG0
760 l32i a1, a1, PT_AREG1
764 l32i a0, a1, PT_AREG0
765 l32i a1, a1, PT_AREG1
768 ENDPROC(kernel_exception)
771 * Debug exception handler.
773 * Currently, we don't support KGDB, so only user application can be debugged.
775 * When we get here, a0 is trashed and saved to excsave[debuglevel]
780 ENTRY(debug_exception)
782 rsr a0, SREG_EPS + XCHAL_DEBUGLEVEL
783 bbsi.l a0, PS_EXCM_BIT, 1f # exception mode
785 /* Set EPC1 and EXCCAUSE */
787 wsr a2, depc # save a2 temporarily
788 rsr a2, SREG_EPC + XCHAL_DEBUGLEVEL
791 movi a2, EXCCAUSE_MAPPED_DEBUG
794 /* Restore PS to the value before the debug exc but with PS.EXCM set.*/
796 movi a2, 1 << PS_EXCM_BIT
800 /* Switch to kernel/user stack, restore jump vector, and save a0 */
802 bbsi.l a2, PS_UM_BIT, 2f # jump if user mode
804 addi a2, a1, -16-PT_SIZE # assume kernel stack
806 l32i a0, a3, DT_DEBUG_SAVE
807 s32i a1, a2, PT_AREG1
808 s32i a0, a2, PT_AREG0
810 s32i a0, a2, PT_DEPC # mark it as a regular exception
811 xsr a3, SREG_EXCSAVE + XCHAL_DEBUGLEVEL
813 s32i a3, a2, PT_AREG3
814 s32i a0, a2, PT_AREG2
817 /* Debug exception is handled as an exception, so interrupts will
818 * likely be enabled in the common exception handler. Disable
819 * preemption if we have HW breakpoints to preserve DEBUGCAUSE.DBNUM
822 #if defined(CONFIG_PREEMPT_COUNT) && defined(CONFIG_HAVE_HW_BREAKPOINT)
823 GET_THREAD_INFO(a2, a1)
824 l32i a3, a2, TI_PRE_COUNT
826 s32i a3, a2, TI_PRE_COUNT
830 bbsi.l a2, PS_UM_BIT, _user_exception
834 l32i a2, a2, EXC_TABLE_KSTK # load kernel stack pointer
837 #ifdef CONFIG_HAVE_HW_BREAKPOINT
838 /* Debug exception while in exception mode. This may happen when
839 * window overflow/underflow handler or fast exception handler hits
840 * data breakpoint, in which case save and disable all data
841 * breakpoints, single-step faulting instruction and restore data
845 bbci.l a0, PS_UM_BIT, 1b # jump if kernel mode
848 bbsi.l a0, DEBUGCAUSE_DBREAK_BIT, .Ldebug_save_dbreak
851 .rept XCHAL_NUM_DBREAK
852 l32i a0, a3, DT_DBREAKC_SAVE + _index * 4
853 wsr a0, SREG_DBREAKC + _index
854 .set _index, _index + 1
857 l32i a0, a3, DT_ICOUNT_LEVEL_SAVE
860 l32i a0, a3, DT_ICOUNT_SAVE
863 l32i a0, a3, DT_DEBUG_SAVE
864 xsr a3, SREG_EXCSAVE + XCHAL_DEBUGLEVEL
869 .rept XCHAL_NUM_DBREAK
871 xsr a0, SREG_DBREAKC + _index
872 s32i a0, a3, DT_DBREAKC_SAVE + _index * 4
873 .set _index, _index + 1
876 movi a0, XCHAL_EXCM_LEVEL + 1
878 s32i a0, a3, DT_ICOUNT_LEVEL_SAVE
882 s32i a0, a3, DT_ICOUNT_SAVE
884 l32i a0, a3, DT_DEBUG_SAVE
885 xsr a3, SREG_EXCSAVE + XCHAL_DEBUGLEVEL
888 /* Debug exception while in exception mode. Should not happen. */
892 ENDPROC(debug_exception)
895 * We get here in case of an unrecoverable exception.
896 * The only thing we can do is to be nice and print a panic message.
897 * We only produce a single stack frame for panic, so ???
902 * - a0 contains the caller address; original value saved in excsave1.
903 * - the original a0 contains a valid return address (backtrace) or 0.
904 * - a2 contains a valid stackpointer
908 * - If the stack pointer could be invalid, the caller has to setup a
909 * dummy stack pointer (e.g. the stack of the init_task)
911 * - If the return address could be invalid, the caller has to set it
912 * to 0, so the backtrace would stop.
917 .ascii "Unrecoverable error in exception handler\0"
921 ENTRY(unrecoverable_exception)
930 movi a1, PS_WOE_MASK | LOCKLEVEL
936 addi a1, a1, PT_REGS_OFFSET
938 movi a6, unrecoverable_text
943 ENDPROC(unrecoverable_exception)
945 /* -------------------------- FAST EXCEPTION HANDLERS ----------------------- */
951 * Fast-handler for alloca exceptions
953 * The ALLOCA handler is entered when user code executes the MOVSP
954 * instruction and the caller's frame is not in the register file.
956 * This algorithm was taken from the Ross Morley's RTOS Porting Layer:
958 * /home/ross/rtos/porting/XtensaRTOS-PortingLayer-20090507/xtensa_vectors.S
960 * It leverages the existing window spill/fill routines and their support for
961 * double exceptions. The 'movsp' instruction will only cause an exception if
962 * the next window needs to be loaded. In fact this ALLOCA exception may be
963 * replaced at some point by changing the hardware to do a underflow exception
964 * of the proper size instead.
966 * This algorithm simply backs out the register changes started by the user
967 * exception handler, makes it appear that we have started a window underflow
968 * by rotating the window back and then setting the old window base (OWB) in
969 * the 'ps' register with the rolled back window base. The 'movsp' instruction
970 * will be re-executed and this time since the next window frames is in the
971 * active AR registers it won't cause an exception.
973 * If the WindowUnderflow code gets a TLB miss the page will get mapped
974 * the partial WindowUnderflow will be handled in the double exception
979 * a0: trashed, original value saved on stack (PT_AREG0)
981 * a2: new stack pointer, original in DEPC
983 * depc: a2, original value saved on stack (PT_DEPC)
984 * excsave_1: dispatch table
986 * PT_DEPC >= VALID_DOUBLE_EXCEPTION_ADDRESS: double exception, DEPC
987 * < VALID_DOUBLE_EXCEPTION_ADDRESS: regular exception
994 extui a3, a2, PS_OWB_SHIFT, PS_OWB_WIDTH
996 l32i a4, a6, PT_AREG0
1000 slli a3, a3, PS_OWB_SHIFT
1009 j _WindowUnderflow12
1010 8: j _WindowUnderflow8
1011 4: j _WindowUnderflow4
1012 ENDPROC(fast_alloca)
1014 #ifdef CONFIG_USER_ABI_CALL0_PROBE
1016 * fast illegal instruction handler.
1018 * This is used to fix up user PS.WOE on the exception caused
1019 * by the first opcode related to register window. If PS.WOE is
1020 * already set it goes directly to the common user exception handler.
1024 * a0: trashed, original value saved on stack (PT_AREG0)
1026 * a2: new stack pointer, original in DEPC
1028 * depc: a2, original value saved on stack (PT_DEPC)
1029 * excsave_1: dispatch table
1032 ENTRY(fast_illegal_instruction_user)
1035 bbsi.l a0, PS_WOE_BIT, 1f
1036 s32i a3, a2, PT_AREG3
1037 movi a3, PS_WOE_MASK
1040 l32i a3, a2, PT_AREG3
1041 l32i a0, a2, PT_AREG0
1045 call0 user_exception
1047 ENDPROC(fast_illegal_instruction_user)
1051 * fast system calls.
1053 * WARNING: The kernel doesn't save the entire user context before
1054 * handling a fast system call. These functions are small and short,
1055 * usually offering some functionality not available to user tasks.
1057 * BE CAREFUL TO PRESERVE THE USER'S CONTEXT.
1061 * a0: trashed, original value saved on stack (PT_AREG0)
1063 * a2: new stack pointer, original in DEPC
1065 * depc: a2, original value saved on stack (PT_DEPC)
1066 * excsave_1: dispatch table
1069 ENTRY(fast_syscall_user)
1077 l32i a0, a2, PT_DEPC
1078 bgeui a0, VALID_DOUBLE_EXCEPTION_ADDRESS, fast_syscall_unrecoverable
1080 rsr a0, depc # get syscall-nr
1081 _beqz a0, fast_syscall_spill_registers
1082 _beqi a0, __NR_xtensa, fast_syscall_xtensa
1084 call0 user_exception
1086 ENDPROC(fast_syscall_user)
1088 ENTRY(fast_syscall_unrecoverable)
1090 /* Restore all states. */
1092 l32i a0, a2, PT_AREG0 # restore a0
1093 xsr a2, depc # restore a2, depc
1096 call0 unrecoverable_exception
1098 ENDPROC(fast_syscall_unrecoverable)
1101 * sysxtensa syscall handler
1103 * int sysxtensa (SYS_XTENSA_ATOMIC_SET, ptr, val, unused);
1104 * int sysxtensa (SYS_XTENSA_ATOMIC_ADD, ptr, val, unused);
1105 * int sysxtensa (SYS_XTENSA_ATOMIC_EXG_ADD, ptr, val, unused);
1106 * int sysxtensa (SYS_XTENSA_ATOMIC_CMP_SWP, ptr, oldval, newval);
1111 * a0: a2 (syscall-nr), original value saved on stack (PT_AREG0)
1113 * a2: new stack pointer, original in a0 and DEPC
1115 * a4..a15: unchanged
1116 * depc: a2, original value saved on stack (PT_DEPC)
1117 * excsave_1: dispatch table
1119 * PT_DEPC >= VALID_DOUBLE_EXCEPTION_ADDRESS: double exception, DEPC
1120 * < VALID_DOUBLE_EXCEPTION_ADDRESS: regular exception
1122 * Note: we don't have to save a2; a2 holds the return value
1127 #ifdef CONFIG_FAST_SYSCALL_XTENSA
1129 ENTRY(fast_syscall_xtensa)
1131 s32i a7, a2, PT_AREG7 # we need an additional register
1132 movi a7, 4 # sizeof(unsigned int)
1133 access_ok a3, a7, a0, a2, .Leac # a0: scratch reg, a2: sp
1135 _bgeui a6, SYS_XTENSA_COUNT, .Lill
1136 _bnei a6, SYS_XTENSA_ATOMIC_CMP_SWP, .Lnswp
1138 /* Fall through for ATOMIC_CMP_SWP. */
1140 .Lswp: /* Atomic compare and swap */
1142 EX(.Leac) l32i a0, a3, 0 # read old value
1143 bne a0, a4, 1f # same as old value? jump
1144 EX(.Leac) s32i a5, a3, 0 # different, modify value
1145 l32i a7, a2, PT_AREG7 # restore a7
1146 l32i a0, a2, PT_AREG0 # restore a0
1147 movi a2, 1 # and return 1
1150 1: l32i a7, a2, PT_AREG7 # restore a7
1151 l32i a0, a2, PT_AREG0 # restore a0
1152 movi a2, 0 # return 0 (note that we cannot set
1155 .Lnswp: /* Atomic set, add, and exg_add. */
1157 EX(.Leac) l32i a7, a3, 0 # orig
1158 addi a6, a6, -SYS_XTENSA_ATOMIC_SET
1159 add a0, a4, a7 # + arg
1160 moveqz a0, a4, a6 # set
1161 addi a6, a6, SYS_XTENSA_ATOMIC_SET
1162 EX(.Leac) s32i a0, a3, 0 # write new value
1166 l32i a7, a0, PT_AREG7 # restore a7
1167 l32i a0, a0, PT_AREG0 # restore a0
1170 .Leac: l32i a7, a2, PT_AREG7 # restore a7
1171 l32i a0, a2, PT_AREG0 # restore a0
1175 .Lill: l32i a7, a2, PT_AREG7 # restore a7
1176 l32i a0, a2, PT_AREG0 # restore a0
1180 ENDPROC(fast_syscall_xtensa)
1182 #else /* CONFIG_FAST_SYSCALL_XTENSA */
1184 ENTRY(fast_syscall_xtensa)
1186 l32i a0, a2, PT_AREG0 # restore a0
1190 ENDPROC(fast_syscall_xtensa)
1192 #endif /* CONFIG_FAST_SYSCALL_XTENSA */
1195 /* fast_syscall_spill_registers.
1199 * a0: trashed, original value saved on stack (PT_AREG0)
1201 * a2: new stack pointer, original in DEPC
1203 * depc: a2, original value saved on stack (PT_DEPC)
1204 * excsave_1: dispatch table
1206 * Note: We assume the stack pointer is EXC_TABLE_KSTK in the fixup handler.
1209 #ifdef CONFIG_FAST_SYSCALL_SPILL_REGISTERS
1211 ENTRY(fast_syscall_spill_registers)
1213 /* Register a FIXUP handler (pass current wb as a parameter) */
1216 movi a0, fast_syscall_spill_registers_fixup
1217 s32i a0, a3, EXC_TABLE_FIXUP
1219 s32i a0, a3, EXC_TABLE_PARAM
1220 xsr a3, excsave1 # restore a3 and excsave_1
1222 /* Save a3, a4 and SAR on stack. */
1225 s32i a3, a2, PT_AREG3
1228 /* The spill routine might clobber a4, a7, a8, a11, a12, and a15. */
1230 s32i a4, a2, PT_AREG4
1231 s32i a7, a2, PT_AREG7
1232 s32i a8, a2, PT_AREG8
1233 s32i a11, a2, PT_AREG11
1234 s32i a12, a2, PT_AREG12
1235 s32i a15, a2, PT_AREG15
1238 * Rotate ws so that the current windowbase is at bit 0.
1239 * Assume ws = xxxwww1yy (www1 current window frame).
1240 * Rotate ws right so that a4 = yyxxxwww1.
1244 rsr a3, windowstart # a3 = xxxwww1yy
1247 or a3, a3, a0 # a3 = xxxwww1yyxxxwww1yy
1248 srl a3, a3 # a3 = 00xxxwww1yyxxxwww1
1250 /* We are done if there are no more than the current register frame. */
1252 extui a3, a3, 1, WSBITS-1 # a3 = 0yyxxxwww
1253 movi a0, (1 << (WSBITS-1))
1254 _beqz a3, .Lnospill # only one active frame? jump
1256 /* We want 1 at the top, so that we return to the current windowbase */
1258 or a3, a3, a0 # 1yyxxxwww
1260 /* Skip empty frames - get 'oldest' WINDOWSTART-bit. */
1262 wsr a3, windowstart # save shifted windowstart
1264 and a3, a0, a3 # first bit set from right: 000010000
1266 ffs_ws a0, a3 # a0: shifts to skip empty frames
1268 sub a0, a3, a0 # WSBITS-a0:number of 0-bits from right
1269 ssr a0 # save in SAR for later.
1277 srl a3, a3 # shift windowstart
1279 /* WB is now just one frame below the oldest frame in the register
1280 window. WS is shifted so the oldest frame is in bit 0, thus, WB
1281 and WS differ by one 4-register frame. */
1283 /* Save frames. Depending what call was used (call4, call8, call12),
1284 * we have to save 4,8. or 12 registers.
1288 .Lloop: _bbsi.l a3, 1, .Lc4
1289 _bbci.l a3, 2, .Lc12
1291 .Lc8: s32e a4, a13, -16
1300 srli a11, a3, 2 # shift windowbase by 2
1305 .Lc4: s32e a4, a9, -16
1315 .Lc12: _bbci.l a3, 3, .Linvalid_mask # bit 2 shouldn't be zero!
1317 /* 12-register frame (call12) */
1332 /* The stack pointer for a4..a7 is out of reach, so we rotate the
1333 * window, grab the stackpointer, and rotate back.
1334 * Alternatively, we could also use the following approach, but that
1335 * makes the fixup routine much more complicated:
1358 /* Done. Do the final rotation and set WS */
1368 /* Advance PC, restore registers and SAR, and return from exception. */
1371 l32i a0, a2, PT_AREG0
1373 l32i a3, a2, PT_AREG3
1375 /* Restore clobbered registers. */
1377 l32i a4, a2, PT_AREG4
1378 l32i a7, a2, PT_AREG7
1379 l32i a8, a2, PT_AREG8
1380 l32i a11, a2, PT_AREG11
1381 l32i a12, a2, PT_AREG12
1382 l32i a15, a2, PT_AREG15
1389 /* We get here because of an unrecoverable error in the window
1390 * registers, so set up a dummy frame and kill the user application.
1391 * Note: We assume EXC_TABLE_KSTK contains a valid stack pointer.
1404 l32i a1, a3, EXC_TABLE_KSTK
1406 movi a4, PS_WOE_MASK | LOCKLEVEL
1413 /* shouldn't return, so panic */
1416 call0 unrecoverable_exception # should not return
1420 ENDPROC(fast_syscall_spill_registers)
1424 * We get here if the spill routine causes an exception, e.g. tlb miss.
1425 * We basically restore WINDOWBASE and WINDOWSTART to the condition when
1426 * we entered the spill routine and jump to the user exception handler.
1428 * Note that we only need to restore the bits in windowstart that have not
1429 * been spilled yet by the _spill_register routine. Luckily, a3 contains a
1430 * rotated windowstart with only those bits set for frames that haven't been
1431 * spilled yet. Because a3 is rotated such that bit 0 represents the register
1432 * frame for the current windowbase - 1, we need to rotate a3 left by the
1433 * value of the current windowbase + 1 and move it to windowstart.
1435 * a0: value of depc, original value in depc
1436 * a2: trashed, original value in EXC_TABLE_DOUBLE_SAVE
1437 * a3: exctable, original value in excsave1
1440 ENTRY(fast_syscall_spill_registers_fixup)
1442 rsr a2, windowbase # get current windowbase (a2 is saved)
1443 xsr a0, depc # restore depc and a0
1444 ssl a2 # set shift (32 - WB)
1446 /* We need to make sure the current registers (a0-a3) are preserved.
1447 * To do this, we simply set the bit for the current window frame
1448 * in WS, so that the exception handlers save them to the task stack.
1450 * Note: we use a3 to set the windowbase, so we take a special care
1451 * of it, saving it in the original _spill_registers frame across
1452 * the exception handler call.
1455 xsr a3, excsave1 # get spill-mask
1456 slli a3, a3, 1 # shift left by one
1457 addi a3, a3, 1 # set the bit for the current window frame
1459 slli a2, a3, 32-WSBITS
1460 src a2, a3, a2 # a2 = xxwww1yyxxxwww1yy......
1461 wsr a2, windowstart # set corrected windowstart
1465 l32i a2, a2, EXC_TABLE_DOUBLE_SAVE # restore a2
1467 s32i a3, a2, EXC_TABLE_DOUBLE_SAVE # save a3
1468 l32i a3, a2, EXC_TABLE_PARAM # original WB (in user task)
1471 /* Return to the original (user task) WINDOWBASE.
1472 * We leave the following frame behind:
1474 * a3: trashed (saved in EXC_TABLE_DOUBLE_SAVE)
1475 * depc: depc (we have to return to that address)
1476 * excsave_1: exctable
1482 /* We are now in the original frame when we entered _spill_registers:
1483 * a0: return address
1484 * a1: used, stack pointer
1485 * a2: kernel stack pointer
1487 * depc: exception address
1489 * Note: This frame might be the same as above.
1492 /* Setup stack pointer. */
1494 addi a2, a2, -PT_USER_SIZE
1495 s32i a0, a2, PT_AREG0
1497 /* Make sure we return to this fixup handler. */
1499 movi a3, fast_syscall_spill_registers_fixup_return
1500 s32i a3, a2, PT_DEPC # setup depc
1502 /* Jump to the exception handler. */
1506 addx4 a0, a0, a3 # find entry in table
1507 l32i a0, a0, EXC_TABLE_FAST_USER # load handler
1508 l32i a3, a3, EXC_TABLE_DOUBLE_SAVE
1511 ENDPROC(fast_syscall_spill_registers_fixup)
1513 ENTRY(fast_syscall_spill_registers_fixup_return)
1515 /* When we return here, all registers have been restored (a2: DEPC) */
1517 wsr a2, depc # exception address
1519 /* Restore fixup handler. */
1522 s32i a3, a2, EXC_TABLE_DOUBLE_SAVE
1523 movi a3, fast_syscall_spill_registers_fixup
1524 s32i a3, a2, EXC_TABLE_FIXUP
1526 s32i a3, a2, EXC_TABLE_PARAM
1527 l32i a2, a2, EXC_TABLE_KSTK
1529 /* Load WB at the time the exception occurred. */
1531 rsr a3, sar # WB is still in SAR
1537 l32i a3, a3, EXC_TABLE_DOUBLE_SAVE
1541 ENDPROC(fast_syscall_spill_registers_fixup_return)
1543 #else /* CONFIG_FAST_SYSCALL_SPILL_REGISTERS */
1545 ENTRY(fast_syscall_spill_registers)
1547 l32i a0, a2, PT_AREG0 # restore a0
1551 ENDPROC(fast_syscall_spill_registers)
1553 #endif /* CONFIG_FAST_SYSCALL_SPILL_REGISTERS */
1557 * We should never get here. Bail out!
1560 ENTRY(fast_second_level_miss_double_kernel)
1563 call0 unrecoverable_exception # should not return
1566 ENDPROC(fast_second_level_miss_double_kernel)
1568 /* First-level entry handler for user, kernel, and double 2nd-level
1569 * TLB miss exceptions. Note that for now, user and kernel miss
1570 * exceptions share the same entry point and are handled identically.
1572 * An old, less-efficient C version of this function used to exist.
1573 * We include it below, interleaved as comments, for reference.
1577 * a0: trashed, original value saved on stack (PT_AREG0)
1579 * a2: new stack pointer, original in DEPC
1581 * depc: a2, original value saved on stack (PT_DEPC)
1582 * excsave_1: dispatch table
1584 * PT_DEPC >= VALID_DOUBLE_EXCEPTION_ADDRESS: double exception, DEPC
1585 * < VALID_DOUBLE_EXCEPTION_ADDRESS: regular exception
1588 ENTRY(fast_second_level_miss)
1590 /* Save a1 and a3. Note: we don't expect a double exception. */
1592 s32i a1, a2, PT_AREG1
1593 s32i a3, a2, PT_AREG3
1595 /* We need to map the page of PTEs for the user task. Find
1596 * the pointer to that page. Also, it's possible for tsk->mm
1597 * to be NULL while tsk->active_mm is nonzero if we faulted on
1598 * a vmalloc address. In that rare case, we must use
1599 * active_mm instead to avoid a fault in this handler. See
1601 * http://mail.nl.linux.org/linux-mm/2002-08/msg00258.html
1602 * (or search Internet on "mm vs. active_mm")
1605 * mm = tsk->active_mm;
1606 * pgd = pgd_offset (mm, regs->excvaddr);
1607 * pmd = pmd_offset (pgd, regs->excvaddr);
1612 l32i a0, a1, TASK_MM # tsk->mm
1615 8: rsr a3, excvaddr # fault address
1616 _PGD_OFFSET(a0, a3, a1)
1617 l32i a0, a0, 0 # read pmdval
1620 /* Read ptevaddr and convert to top of page-table page.
1622 * vpnval = read_ptevaddr_register() & PAGE_MASK;
1623 * vpnval += DTLB_WAY_PGTABLE;
1624 * pteval = mk_pte (virt_to_page(pmd_val(pmdval)), PAGE_KERNEL);
1625 * write_dtlb_entry (pteval, vpnval);
1627 * The messy computation for 'pteval' above really simplifies
1628 * into the following:
1630 * pteval = ((pmdval - PAGE_OFFSET + PHYS_OFFSET) & PAGE_MASK)
1634 movi a1, (PHYS_OFFSET - PAGE_OFFSET) & 0xffffffff
1635 add a0, a0, a1 # pmdval - PAGE_OFFSET
1636 extui a1, a0, 0, PAGE_SHIFT # ... & PAGE_MASK
1639 movi a1, _PAGE_DIRECTORY
1640 or a0, a0, a1 # ... | PAGE_DIRECTORY
1643 * We utilize all three wired-ways (7-9) to hold pmd translations.
1644 * Memory regions are mapped to the DTLBs according to bits 28 and 29.
1645 * This allows to map the three most common regions to three different
1647 * 0,1 -> way 7 program (0040.0000) and virtual (c000.0000)
1648 * 2 -> way 8 shared libaries (2000.0000)
1649 * 3 -> way 0 stack (3000.0000)
1652 extui a3, a3, 28, 2 # addr. bit 28 and 29 0,1,2,3
1654 addx2 a3, a3, a3 # -> 0,3,6,9
1655 srli a1, a1, PAGE_SHIFT
1656 extui a3, a3, 2, 2 # -> 0,0,1,2
1657 slli a1, a1, PAGE_SHIFT # ptevaddr & PAGE_MASK
1658 addi a3, a3, DTLB_WAY_PGD
1659 add a1, a1, a3 # ... + way_number
1664 /* Exit critical section. */
1668 s32i a0, a3, EXC_TABLE_FIXUP
1670 /* Restore the working registers, and return. */
1672 l32i a0, a2, PT_AREG0
1673 l32i a1, a2, PT_AREG1
1674 l32i a3, a2, PT_AREG3
1675 l32i a2, a2, PT_DEPC
1677 bgeui a2, VALID_DOUBLE_EXCEPTION_ADDRESS, 1f
1679 /* Restore excsave1 and return. */
1684 /* Return from double exception. */
1690 9: l32i a0, a1, TASK_ACTIVE_MM # unlikely case mm == 0
1693 /* Even more unlikely case active_mm == 0.
1694 * We can get here with NMI in the middle of context_switch that
1695 * touches vmalloc area.
1700 #if (DCACHE_WAY_SIZE > PAGE_SIZE)
1702 2: /* Special case for cache aliasing.
1703 * We (should) only get here if a clear_user_page, copy_user_page
1704 * or the aliased cache flush functions got preemptively interrupted
1705 * by another task. Re-establish temporary mapping to the
1706 * TLBTEMP_BASE areas.
1709 /* We shouldn't be in a double exception */
1711 l32i a0, a2, PT_DEPC
1712 bgeui a0, VALID_DOUBLE_EXCEPTION_ADDRESS, 2f
1714 /* Make sure the exception originated in the special functions */
1716 movi a0, __tlbtemp_mapping_start
1719 movi a0, __tlbtemp_mapping_end
1722 /* Check if excvaddr was in one of the TLBTEMP_BASE areas. */
1724 movi a3, TLBTEMP_BASE_1
1728 addi a1, a0, -TLBTEMP_SIZE
1731 /* Check if we have to restore an ITLB mapping. */
1733 movi a1, __tlbtemp_mapping_itlb
1742 /* Jump for ITLB entry */
1746 /* We can use up to two TLBTEMP areas, one for src and one for dst. */
1748 extui a3, a0, PAGE_SHIFT + DCACHE_ALIAS_ORDER, 1
1751 /* PPN is in a6 for the first TLBTEMP area and in a7 for the second. */
1757 /* ITLB entry. We only use dst in a6. */
1764 #endif // DCACHE_WAY_SIZE > PAGE_SIZE
1767 2: /* Invalid PGD, default exception handling */
1770 s32i a1, a2, PT_AREG2
1774 bbsi.l a2, PS_UM_BIT, 1f
1775 call0 _kernel_exception
1776 1: call0 _user_exception
1778 ENDPROC(fast_second_level_miss)
1781 * StoreProhibitedException
1783 * Update the pte and invalidate the itlb mapping for this pte.
1787 * a0: trashed, original value saved on stack (PT_AREG0)
1789 * a2: new stack pointer, original in DEPC
1791 * depc: a2, original value saved on stack (PT_DEPC)
1792 * excsave_1: dispatch table
1794 * PT_DEPC >= VALID_DOUBLE_EXCEPTION_ADDRESS: double exception, DEPC
1795 * < VALID_DOUBLE_EXCEPTION_ADDRESS: regular exception
1798 ENTRY(fast_store_prohibited)
1800 /* Save a1 and a3. */
1802 s32i a1, a2, PT_AREG1
1803 s32i a3, a2, PT_AREG3
1806 l32i a0, a1, TASK_MM # tsk->mm
1809 8: rsr a1, excvaddr # fault address
1810 _PGD_OFFSET(a0, a1, a3)
1815 * Note that we test _PAGE_WRITABLE_BIT only if PTE is present
1816 * and is not PAGE_NONE. See pgtable.h for possible PTE layouts.
1819 _PTE_OFFSET(a0, a1, a3)
1820 l32i a3, a0, 0 # read pteval
1821 movi a1, _PAGE_CA_INVALID
1823 bbci.l a3, _PAGE_WRITABLE_BIT, 2f
1825 movi a1, _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_HW_WRITE
1830 /* We need to flush the cache if we have page coloring. */
1831 #if (DCACHE_WAY_SIZE > PAGE_SIZE) && XCHAL_DCACHE_IS_WRITEBACK
1837 /* Exit critical section. */
1841 s32i a0, a3, EXC_TABLE_FIXUP
1843 /* Restore the working registers, and return. */
1845 l32i a3, a2, PT_AREG3
1846 l32i a1, a2, PT_AREG1
1847 l32i a0, a2, PT_AREG0
1848 l32i a2, a2, PT_DEPC
1850 bgeui a2, VALID_DOUBLE_EXCEPTION_ADDRESS, 1f
1855 /* Double exception. Restore FIXUP handler and return. */
1861 9: l32i a0, a1, TASK_ACTIVE_MM # unlikely case mm == 0
1864 2: /* If there was a problem, handle fault in C */
1866 rsr a3, depc # still holds a2
1867 s32i a3, a2, PT_AREG2
1871 bbsi.l a2, PS_UM_BIT, 1f
1872 call0 _kernel_exception
1873 1: call0 _user_exception
1875 ENDPROC(fast_store_prohibited)
1877 #endif /* CONFIG_MMU */
1883 * void system_call (struct pt_regs* regs, int exccause)
1892 /* regs->syscall = regs->areg[2] */
1894 l32i a7, a2, PT_AREG2
1895 s32i a7, a2, PT_SYSCALL
1897 GET_THREAD_INFO(a4, a1)
1898 l32i a3, a4, TI_FLAGS
1899 movi a4, _TIF_WORK_MASK
1904 call4 do_syscall_trace_enter
1905 beqz a6, .Lsyscall_exit
1906 l32i a7, a2, PT_SYSCALL
1909 /* syscall = sys_call_table[syscall_nr] */
1911 movi a4, sys_call_table
1912 movi a5, __NR_syscalls
1919 /* Load args: arg0 - arg5 are passed via regs. */
1921 l32i a6, a2, PT_AREG6
1922 l32i a7, a2, PT_AREG3
1923 l32i a8, a2, PT_AREG4
1924 l32i a9, a2, PT_AREG5
1925 l32i a10, a2, PT_AREG8
1926 l32i a11, a2, PT_AREG9
1930 1: /* regs->areg[2] = return_value */
1932 s32i a6, a2, PT_AREG2
1939 call4 do_syscall_trace_leave
1942 ENDPROC(system_call)
1945 * Spill live registers on the kernel stack macro.
1947 * Entry condition: ps.woe is set, ps.excm is cleared
1948 * Exit condition: windowstart has single bit set
1949 * May clobber: a12, a13
1951 .macro spill_registers_kernel
1953 #if XCHAL_NUM_AREGS > 16
1961 #if XCHAL_NUM_AREGS > 32
1962 .rept (XCHAL_NUM_AREGS - 32) / 12
1968 #if XCHAL_NUM_AREGS % 12 == 0
1970 #elif XCHAL_NUM_AREGS % 12 == 4
1972 #elif XCHAL_NUM_AREGS % 12 == 8
1985 * struct task* _switch_to (struct task* prev, struct task* next)
1991 abi_entry(XTENSA_SPILL_STACK_RESERVE)
1993 mov a11, a3 # and 'next' (a3)
1995 l32i a4, a2, TASK_THREAD_INFO
1996 l32i a5, a3, TASK_THREAD_INFO
1998 save_xtregs_user a4 a6 a8 a9 a12 a13 THREAD_XTREGS_USER
2000 #if THREAD_RA > 1020 || THREAD_SP > 1020
2001 addi a10, a2, TASK_THREAD
2002 s32i a0, a10, THREAD_RA - TASK_THREAD # save return address
2003 s32i a1, a10, THREAD_SP - TASK_THREAD # save stack pointer
2005 s32i a0, a2, THREAD_RA # save return address
2006 s32i a1, a2, THREAD_SP # save stack pointer
2009 #if defined(CONFIG_STACKPROTECTOR) && !defined(CONFIG_SMP)
2010 movi a6, __stack_chk_guard
2011 l32i a8, a3, TASK_STACK_CANARY
2015 /* Disable ints while we manipulate the stack pointer. */
2020 /* Switch CPENABLE */
2022 #if (XTENSA_HAVE_COPROCESSORS || XTENSA_HAVE_IO_PORTS)
2023 l32i a3, a5, THREAD_CPENABLE
2025 s32i a3, a4, THREAD_CPENABLE
2028 #if XCHAL_HAVE_EXCLUSIVE
2029 l32i a3, a5, THREAD_ATOMCTL8
2031 s32i a3, a4, THREAD_ATOMCTL8
2034 /* Flush register file. */
2036 spill_registers_kernel
2038 /* Set kernel stack (and leave critical section)
2039 * Note: It's save to set it here. The stack will not be overwritten
2040 * because the kernel stack will only be loaded again after
2041 * we return from kernel space.
2044 rsr a3, excsave1 # exc_table
2045 addi a7, a5, PT_REGS_OFFSET
2046 s32i a7, a3, EXC_TABLE_KSTK
2048 /* restore context of the task 'next' */
2050 l32i a0, a11, THREAD_RA # restore return address
2051 l32i a1, a11, THREAD_SP # restore stack pointer
2053 load_xtregs_user a5 a6 a8 a9 a12 a13 THREAD_XTREGS_USER
2058 abi_ret(XTENSA_SPILL_STACK_RESERVE)
2062 ENTRY(ret_from_fork)
2064 /* void schedule_tail (struct task_struct *prev)
2065 * Note: prev is still in a6 (return value from fake call4 frame)
2070 call4 do_syscall_trace_leave
2072 j common_exception_return
2074 ENDPROC(ret_from_fork)
2077 * Kernel thread creation helper
2078 * On entry, set up by copy_thread: a2 = thread_fn, a3 = thread_fn arg
2079 * left from _switch_to: a6 = prev
2081 ENTRY(ret_from_kernel_thread)
2086 j common_exception_return
2088 ENDPROC(ret_from_kernel_thread)