2 * arch/xtensa/kernel/coprocessor.S
4 * Xtensa processor configuration-specific table of coprocessor and
5 * other custom register layout information.
7 * This file is subject to the terms and conditions of the GNU General Public
8 * License. See the file "COPYING" in the main directory of this archive
11 * Copyright (C) 2003 - 2007 Tensilica Inc.
15 #include <linux/linkage.h>
16 #include <asm/asm-offsets.h>
17 #include <asm/asmmacro.h>
18 #include <asm/coprocessor.h>
19 #include <asm/current.h>
22 #if XTENSA_HAVE_COPROCESSORS
25 * Macros for lazy context switch.
28 #define SAVE_CP_REGS(x) \
29 .if XTENSA_HAVE_COPROCESSOR(x); \
31 .Lsave_cp_regs_cp##x: \
32 xchal_cp##x##_store a2 a3 a4 a5 a6; \
36 #define SAVE_CP_REGS_TAB(x) \
37 .if XTENSA_HAVE_COPROCESSOR(x); \
38 .long .Lsave_cp_regs_cp##x; \
42 .long THREAD_XTREGS_CP##x
45 #define LOAD_CP_REGS(x) \
46 .if XTENSA_HAVE_COPROCESSOR(x); \
48 .Lload_cp_regs_cp##x: \
49 xchal_cp##x##_load a2 a3 a4 a5 a6; \
53 #define LOAD_CP_REGS_TAB(x) \
54 .if XTENSA_HAVE_COPROCESSOR(x); \
55 .long .Lload_cp_regs_cp##x; \
59 .long THREAD_XTREGS_CP##x
82 .Lsave_cp_regs_jump_table:
92 .Lload_cp_regs_jump_table:
105 * a0: trashed, original value saved on stack (PT_AREG0)
107 * a2: new stack pointer, original in DEPC
109 * depc: a2, original value saved on stack (PT_DEPC)
110 * excsave_1: dispatch table
112 * PT_DEPC >= VALID_DOUBLE_EXCEPTION_ADDRESS: double exception, DEPC
113 * < VALID_DOUBLE_EXCEPTION_ADDRESS: regular exception
116 ENTRY(fast_coprocessor)
118 /* Save remaining registers a1-a3 and SAR */
120 s32i a3, a2, PT_AREG3
122 s32i a1, a2, PT_AREG1
126 s32i a2, a1, PT_AREG2
129 * The hal macros require up to 4 temporary registers. We use a3..a6.
132 s32i a4, a1, PT_AREG4
133 s32i a5, a1, PT_AREG5
134 s32i a6, a1, PT_AREG6
136 /* Find coprocessor number. Subtract first CP EXCCAUSE from EXCCAUSE */
139 addi a3, a3, -EXCCAUSE_COPROCESSOR0_DISABLED
141 /* Set corresponding CPENABLE bit -> (sar:cp-index, a3: 1<<cp-index)*/
143 ssl a3 # SAR: 32 - coprocessor_number
151 /* Retrieve previous owner. (a3 still holds CP number) */
153 movi a0, coprocessor_owner # list of owners
154 addx4 a0, a3, a0 # entry for CP
157 beqz a4, 1f # skip 'save' if no previous owner
159 /* Disable coprocessor for previous owner. (a2 = 1 << CP number) */
161 l32i a5, a4, THREAD_CPENABLE
162 xor a5, a5, a2 # (1 << cp-id) still in a2
163 s32i a5, a4, THREAD_CPENABLE
166 * Get context save area and 'call' save routine.
167 * (a4 still holds previous owner (thread_info), a3 CP number)
170 movi a5, .Lsave_cp_regs_jump_table
171 movi a0, 2f # a0: 'return' address
172 addx8 a3, a3, a5 # a3: coprocessor number
173 l32i a2, a3, 4 # a2: xtregs offset
174 l32i a3, a3, 0 # a3: jump address
178 /* Note that only a0 and a1 were preserved. */
181 addi a3, a3, -EXCCAUSE_COPROCESSOR0_DISABLED
182 movi a0, coprocessor_owner
185 /* Set new 'owner' (a0 points to the CP owner, a3 contains the CP nr) */
187 1: GET_THREAD_INFO (a4, a1)
190 /* Get context save area and 'call' load routine. */
192 movi a5, .Lload_cp_regs_jump_table
195 l32i a2, a3, 4 # a2: xtregs offset
196 l32i a3, a3, 0 # a3: jump address
200 /* Restore all registers and return from exception handler. */
202 1: l32i a6, a1, PT_AREG6
203 l32i a5, a1, PT_AREG5
204 l32i a4, a1, PT_AREG4
207 l32i a3, a1, PT_AREG3
208 l32i a2, a1, PT_AREG2
210 l32i a0, a1, PT_AREG0
211 l32i a1, a1, PT_AREG1
215 ENDPROC(fast_coprocessor)
220 * coprocessor_flush(struct thread_info*, index)
223 * Save coprocessor registers for coprocessor 'index'.
224 * The register values are saved to or loaded from the coprocessor area
225 * inside the task_info structure.
227 * Note that this function doesn't update the coprocessor_owner information!
231 ENTRY(coprocessor_flush)
233 /* reserve 4 bytes on stack to save a0 */
237 movi a0, .Lsave_cp_regs_jump_table
248 ENDPROC(coprocessor_flush)
252 ENTRY(coprocessor_owner)
254 .fill XCHAL_CP_MAX, 4, 0
256 END(coprocessor_owner)
258 #endif /* XTENSA_HAVE_COPROCESSORS */