2 * arch/xtensa/include/asm/traps.h
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file "COPYING" in the main directory of this archive
8 * Copyright (C) 2012 Tensilica Inc.
10 #ifndef _XTENSA_TRAPS_H
11 #define _XTENSA_TRAPS_H
13 #include <asm/ptrace.h>
16 * handler must be either of the following:
17 * void (*)(struct pt_regs *regs);
18 * void (*)(struct pt_regs *regs, unsigned long exccause);
20 extern void * __init trap_set_handler(int cause, void *handler);
21 extern void do_unhandled(struct pt_regs *regs, unsigned long exccause);
22 void secondary_trap_init(void);
24 static inline void spill_registers(void)
26 #if XCHAL_NUM_AREGS > 16
27 __asm__ __volatile__ (
33 #if XCHAL_NUM_AREGS == 32
45 " .rept (" __stringify(XCHAL_NUM_AREGS) " - 16) / 12\n"
50 #if XCHAL_NUM_AREGS % 12 == 0
52 #elif XCHAL_NUM_AREGS % 12 == 4
54 #elif XCHAL_NUM_AREGS % 12 == 8
60 : : : "a8", "a9", "memory");
62 __asm__ __volatile__ (
69 /* Pointer to debug exception handler */
70 void (*debug_exception)(void);
71 /* Temporary register save area */
72 unsigned long debug_save[1];
73 #ifdef CONFIG_HAVE_HW_BREAKPOINT
74 /* Save area for DBREAKC registers */
75 unsigned long dbreakc_save[XCHAL_NUM_DBREAK];
76 /* Saved ICOUNT register */
77 unsigned long icount_save;
78 /* Saved ICOUNTLEVEL register */
79 unsigned long icount_level_save;
83 void debug_exception(void);
85 #endif /* _XTENSA_TRAPS_H */