2 * arch/xtensa/include/asm/traps.h
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file "COPYING" in the main directory of this archive
8 * Copyright (C) 2012 Tensilica Inc.
10 #ifndef _XTENSA_TRAPS_H
11 #define _XTENSA_TRAPS_H
13 #include <asm/ptrace.h>
15 typedef void xtensa_exception_handler(struct pt_regs *regs);
18 * Per-CPU exception handling data structure.
19 * EXCSAVE1 points to it.
24 /* Double exception save area for a0 */
25 unsigned long double_save;
28 /* For passing a parameter to fixup */
30 #if XTENSA_HAVE_COPROCESSORS
31 /* Pointers to owner struct thread_info */
32 struct thread_info *coprocessor_owner[XCHAL_CP_MAX];
34 /* Fast user exception handlers */
35 void *fast_user_handler[EXCCAUSE_N];
36 /* Fast kernel exception handlers */
37 void *fast_kernel_handler[EXCCAUSE_N];
38 /* Default C-Handlers */
39 xtensa_exception_handler *default_handler[EXCCAUSE_N];
42 DECLARE_PER_CPU(struct exc_table, exc_table);
44 xtensa_exception_handler *
45 __init trap_set_handler(int cause, xtensa_exception_handler *handler);
47 asmlinkage void fast_illegal_instruction_user(void);
48 asmlinkage void fast_syscall_user(void);
49 asmlinkage void fast_alloca(void);
50 asmlinkage void fast_load_store(void);
51 asmlinkage void fast_unaligned(void);
52 asmlinkage void fast_second_level_miss(void);
53 asmlinkage void fast_store_prohibited(void);
54 asmlinkage void fast_coprocessor(void);
56 asmlinkage void kernel_exception(void);
57 asmlinkage void user_exception(void);
58 asmlinkage void system_call(struct pt_regs *regs);
60 void do_IRQ(int hwirq, struct pt_regs *regs);
61 void do_page_fault(struct pt_regs *regs);
62 void do_unhandled(struct pt_regs *regs);
64 /* Initialize minimal exc_table structure sufficient for basic paging */
65 static inline void __init early_trap_init(void)
67 static struct exc_table init_exc_table __initdata = {
68 #ifdef CONFIG_XTENSA_LOAD_STORE
69 .fast_kernel_handler[EXCCAUSE_LOAD_STORE_ERROR] =
73 .fast_kernel_handler[EXCCAUSE_DTLB_MISS] =
74 fast_second_level_miss,
77 xtensa_set_sr(&init_exc_table, excsave1);
80 void secondary_trap_init(void);
82 static inline void spill_registers(void)
84 #if defined(__XTENSA_WINDOWED_ABI__)
85 #if XCHAL_NUM_AREGS > 16
86 __asm__ __volatile__ (
92 #if XCHAL_NUM_AREGS == 32
104 " .rept (" __stringify(XCHAL_NUM_AREGS) " - 16) / 12\n"
109 #if XCHAL_NUM_AREGS % 12 == 0
111 #elif XCHAL_NUM_AREGS % 12 == 4
113 #elif XCHAL_NUM_AREGS % 12 == 8
119 : : : "a8", "a9", "memory");
121 __asm__ __volatile__ (
129 /* Pointer to debug exception handler */
130 void (*debug_exception)(void);
131 /* Temporary register save area */
132 unsigned long debug_save[1];
133 #ifdef CONFIG_HAVE_HW_BREAKPOINT
134 /* Save area for DBREAKC registers */
135 unsigned long dbreakc_save[XCHAL_NUM_DBREAK];
136 /* Saved ICOUNT register */
137 unsigned long icount_save;
138 /* Saved ICOUNTLEVEL register */
139 unsigned long icount_level_save;
143 void debug_exception(void);
145 #endif /* _XTENSA_TRAPS_H */