2 * include/asm-xtensa/atomic.h
4 * Atomic operations that C can't guarantee us. Useful for resource counting..
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
10 * Copyright (C) 2001 - 2008 Tensilica Inc.
13 #ifndef _XTENSA_ATOMIC_H
14 #define _XTENSA_ATOMIC_H
16 #include <linux/stringify.h>
17 #include <linux/types.h>
20 #include <asm/processor.h>
21 #include <asm/cmpxchg.h>
22 #include <asm/barrier.h>
24 #define ATOMIC_INIT(i) { (i) }
27 * This Xtensa implementation assumes that the right mechanism
28 * for exclusion is for locking interrupts to level EXCM_LEVEL.
30 * Locking interrupts looks like this:
37 * Note that a15 is used here because the register allocation
38 * done by the compiler is not guaranteed and a window overflow
39 * may not occur between the rsil and wsr instructions. By using
40 * a15 in the rsil, the machine is guaranteed to be in a state
41 * where no register reference will cause an overflow.
45 * atomic_read - read atomic variable
46 * @v: pointer of type atomic_t
48 * Atomically reads the value of @v.
50 #define atomic_read(v) READ_ONCE((v)->counter)
53 * atomic_set - set atomic variable
54 * @v: pointer of type atomic_t
57 * Atomically sets the value of @v to @i.
59 #define atomic_set(v,i) WRITE_ONCE((v)->counter, (i))
62 #define ATOMIC_OP(op) \
63 static inline void atomic_##op(int i, atomic_t * v) \
68 __asm__ __volatile__( \
69 "1: l32i %1, %3, 0\n" \
70 " wsr %1, scompare1\n" \
71 " " #op " %0, %1, %2\n" \
72 " s32c1i %0, %3, 0\n" \
74 : "=&a" (result), "=&a" (tmp) \
80 #define ATOMIC_OP_RETURN(op) \
81 static inline int atomic_##op##_return(int i, atomic_t * v) \
86 __asm__ __volatile__( \
87 "1: l32i %1, %3, 0\n" \
88 " wsr %1, scompare1\n" \
89 " " #op " %0, %1, %2\n" \
90 " s32c1i %0, %3, 0\n" \
92 " " #op " %0, %0, %2\n" \
93 : "=&a" (result), "=&a" (tmp) \
101 #define ATOMIC_FETCH_OP(op) \
102 static inline int atomic_fetch_##op(int i, atomic_t * v) \
107 __asm__ __volatile__( \
108 "1: l32i %1, %3, 0\n" \
109 " wsr %1, scompare1\n" \
110 " " #op " %0, %1, %2\n" \
111 " s32c1i %0, %3, 0\n" \
112 " bne %0, %1, 1b\n" \
113 : "=&a" (result), "=&a" (tmp) \
121 #else /* XCHAL_HAVE_S32C1I */
123 #define ATOMIC_OP(op) \
124 static inline void atomic_##op(int i, atomic_t * v) \
128 __asm__ __volatile__( \
129 " rsil a15, "__stringify(TOPLEVEL)"\n"\
130 " l32i %0, %2, 0\n" \
131 " " #op " %0, %0, %1\n" \
132 " s32i %0, %2, 0\n" \
141 #define ATOMIC_OP_RETURN(op) \
142 static inline int atomic_##op##_return(int i, atomic_t * v) \
146 __asm__ __volatile__( \
147 " rsil a15,"__stringify(TOPLEVEL)"\n" \
148 " l32i %0, %2, 0\n" \
149 " " #op " %0, %0, %1\n" \
150 " s32i %0, %2, 0\n" \
161 #define ATOMIC_FETCH_OP(op) \
162 static inline int atomic_fetch_##op(int i, atomic_t * v) \
164 unsigned int tmp, vval; \
166 __asm__ __volatile__( \
167 " rsil a15,"__stringify(TOPLEVEL)"\n" \
168 " l32i %0, %3, 0\n" \
169 " " #op " %1, %0, %2\n" \
170 " s32i %1, %3, 0\n" \
173 : "=&a" (vval), "=&a" (tmp) \
181 #endif /* XCHAL_HAVE_S32C1I */
183 #define ATOMIC_OPS(op) ATOMIC_OP(op) ATOMIC_FETCH_OP(op) ATOMIC_OP_RETURN(op)
189 #define ATOMIC_OPS(op) ATOMIC_OP(op) ATOMIC_FETCH_OP(op)
196 #undef ATOMIC_FETCH_OP
197 #undef ATOMIC_OP_RETURN
200 #define atomic_cmpxchg(v, o, n) ((int)cmpxchg(&((v)->counter), (o), (n)))
201 #define atomic_xchg(v, new) (xchg(&((v)->counter), new))
203 #endif /* __KERNEL__ */
205 #endif /* _XTENSA_ATOMIC_H */