2 * include/asm-xtensa/atomic.h
4 * Atomic operations that C can't guarantee us. Useful for resource counting..
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
10 * Copyright (C) 2001 - 2008 Tensilica Inc.
13 #ifndef _XTENSA_ATOMIC_H
14 #define _XTENSA_ATOMIC_H
16 #include <linux/stringify.h>
17 #include <linux/types.h>
18 #include <asm/processor.h>
19 #include <asm/cmpxchg.h>
20 #include <asm/barrier.h>
23 * This Xtensa implementation assumes that the right mechanism
24 * for exclusion is for locking interrupts to level EXCM_LEVEL.
26 * Locking interrupts looks like this:
33 * Note that a14 is used here because the register allocation
34 * done by the compiler is not guaranteed and a window overflow
35 * may not occur between the rsil and wsr instructions. By using
36 * a14 in the rsil, the machine is guaranteed to be in a state
37 * where no register reference will cause an overflow.
41 * atomic_read - read atomic variable
42 * @v: pointer of type atomic_t
44 * Atomically reads the value of @v.
46 #define arch_atomic_read(v) READ_ONCE((v)->counter)
49 * atomic_set - set atomic variable
50 * @v: pointer of type atomic_t
53 * Atomically sets the value of @v to @i.
55 #define arch_atomic_set(v,i) WRITE_ONCE((v)->counter, (i))
57 #if XCHAL_HAVE_EXCLUSIVE
58 #define ATOMIC_OP(op) \
59 static inline void arch_atomic_##op(int i, atomic_t *v) \
64 __asm__ __volatile__( \
65 "1: l32ex %[tmp], %[addr]\n" \
66 " " #op " %[result], %[tmp], %[i]\n" \
67 " s32ex %[result], %[addr]\n" \
68 " getex %[result]\n" \
69 " beqz %[result], 1b\n" \
70 : [result] "=&a" (result), [tmp] "=&a" (tmp) \
71 : [i] "a" (i), [addr] "a" (v) \
76 #define ATOMIC_OP_RETURN(op) \
77 static inline int arch_atomic_##op##_return(int i, atomic_t *v) \
82 __asm__ __volatile__( \
83 "1: l32ex %[tmp], %[addr]\n" \
84 " " #op " %[result], %[tmp], %[i]\n" \
85 " s32ex %[result], %[addr]\n" \
86 " getex %[result]\n" \
87 " beqz %[result], 1b\n" \
88 " " #op " %[result], %[tmp], %[i]\n" \
89 : [result] "=&a" (result), [tmp] "=&a" (tmp) \
90 : [i] "a" (i), [addr] "a" (v) \
97 #define ATOMIC_FETCH_OP(op) \
98 static inline int arch_atomic_fetch_##op(int i, atomic_t *v) \
103 __asm__ __volatile__( \
104 "1: l32ex %[tmp], %[addr]\n" \
105 " " #op " %[result], %[tmp], %[i]\n" \
106 " s32ex %[result], %[addr]\n" \
107 " getex %[result]\n" \
108 " beqz %[result], 1b\n" \
109 : [result] "=&a" (result), [tmp] "=&a" (tmp) \
110 : [i] "a" (i), [addr] "a" (v) \
117 #elif XCHAL_HAVE_S32C1I
118 #define ATOMIC_OP(op) \
119 static inline void arch_atomic_##op(int i, atomic_t * v) \
124 __asm__ __volatile__( \
125 "1: l32i %[tmp], %[mem]\n" \
126 " wsr %[tmp], scompare1\n" \
127 " " #op " %[result], %[tmp], %[i]\n" \
128 " s32c1i %[result], %[mem]\n" \
129 " bne %[result], %[tmp], 1b\n" \
130 : [result] "=&a" (result), [tmp] "=&a" (tmp), \
137 #define ATOMIC_OP_RETURN(op) \
138 static inline int arch_atomic_##op##_return(int i, atomic_t * v) \
143 __asm__ __volatile__( \
144 "1: l32i %[tmp], %[mem]\n" \
145 " wsr %[tmp], scompare1\n" \
146 " " #op " %[result], %[tmp], %[i]\n" \
147 " s32c1i %[result], %[mem]\n" \
148 " bne %[result], %[tmp], 1b\n" \
149 " " #op " %[result], %[result], %[i]\n" \
150 : [result] "=&a" (result), [tmp] "=&a" (tmp), \
159 #define ATOMIC_FETCH_OP(op) \
160 static inline int arch_atomic_fetch_##op(int i, atomic_t * v) \
165 __asm__ __volatile__( \
166 "1: l32i %[tmp], %[mem]\n" \
167 " wsr %[tmp], scompare1\n" \
168 " " #op " %[result], %[tmp], %[i]\n" \
169 " s32c1i %[result], %[mem]\n" \
170 " bne %[result], %[tmp], 1b\n" \
171 : [result] "=&a" (result), [tmp] "=&a" (tmp), \
180 #else /* XCHAL_HAVE_S32C1I */
182 #define ATOMIC_OP(op) \
183 static inline void arch_atomic_##op(int i, atomic_t * v) \
187 __asm__ __volatile__( \
188 " rsil a14, "__stringify(TOPLEVEL)"\n" \
189 " l32i %[result], %[mem]\n" \
190 " " #op " %[result], %[result], %[i]\n" \
191 " s32i %[result], %[mem]\n" \
194 : [result] "=&a" (vval), [mem] "+m" (*v) \
200 #define ATOMIC_OP_RETURN(op) \
201 static inline int arch_atomic_##op##_return(int i, atomic_t * v) \
205 __asm__ __volatile__( \
206 " rsil a14,"__stringify(TOPLEVEL)"\n" \
207 " l32i %[result], %[mem]\n" \
208 " " #op " %[result], %[result], %[i]\n" \
209 " s32i %[result], %[mem]\n" \
212 : [result] "=&a" (vval), [mem] "+m" (*v) \
220 #define ATOMIC_FETCH_OP(op) \
221 static inline int arch_atomic_fetch_##op(int i, atomic_t * v) \
223 unsigned int tmp, vval; \
225 __asm__ __volatile__( \
226 " rsil a14,"__stringify(TOPLEVEL)"\n" \
227 " l32i %[result], %[mem]\n" \
228 " " #op " %[tmp], %[result], %[i]\n" \
229 " s32i %[tmp], %[mem]\n" \
232 : [result] "=&a" (vval), [tmp] "=&a" (tmp), \
241 #endif /* XCHAL_HAVE_S32C1I */
243 #define ATOMIC_OPS(op) ATOMIC_OP(op) ATOMIC_FETCH_OP(op) ATOMIC_OP_RETURN(op)
248 #define arch_atomic_add_return arch_atomic_add_return
249 #define arch_atomic_sub_return arch_atomic_sub_return
250 #define arch_atomic_fetch_add arch_atomic_fetch_add
251 #define arch_atomic_fetch_sub arch_atomic_fetch_sub
254 #define ATOMIC_OPS(op) ATOMIC_OP(op) ATOMIC_FETCH_OP(op)
260 #define arch_atomic_fetch_and arch_atomic_fetch_and
261 #define arch_atomic_fetch_or arch_atomic_fetch_or
262 #define arch_atomic_fetch_xor arch_atomic_fetch_xor
265 #undef ATOMIC_FETCH_OP
266 #undef ATOMIC_OP_RETURN
269 #endif /* _XTENSA_ATOMIC_H */