1 // SPDX-License-Identifier: GPL-2.0-only
3 * Suspend support specific for i386/x86-64.
5 * Copyright (c) 2007 Rafael J. Wysocki <rjw@sisk.pl>
6 * Copyright (c) 2002 Pavel Machek <pavel@ucw.cz>
7 * Copyright (c) 2001 Patrick Mochel <mochel@osdl.org>
10 #include <linux/suspend.h>
11 #include <linux/export.h>
12 #include <linux/smp.h>
13 #include <linux/perf_event.h>
14 #include <linux/tboot.h>
15 #include <linux/dmi.h>
16 #include <linux/pgtable.h>
18 #include <asm/proto.h>
22 #include <asm/suspend.h>
23 #include <asm/fpu/api.h>
24 #include <asm/debugreg.h>
26 #include <asm/mmu_context.h>
27 #include <asm/cpu_device_id.h>
28 #include <asm/microcode.h>
31 __visible unsigned long saved_context_ebx;
32 __visible unsigned long saved_context_esp, saved_context_ebp;
33 __visible unsigned long saved_context_esi, saved_context_edi;
34 __visible unsigned long saved_context_eflags;
36 struct saved_context saved_context;
38 static void msr_save_context(struct saved_context *ctxt)
40 struct saved_msr *msr = ctxt->saved_msrs.array;
41 struct saved_msr *end = msr + ctxt->saved_msrs.num;
45 rdmsrl(msr->info.msr_no, msr->info.reg.q);
50 static void msr_restore_context(struct saved_context *ctxt)
52 struct saved_msr *msr = ctxt->saved_msrs.array;
53 struct saved_msr *end = msr + ctxt->saved_msrs.num;
57 wrmsrl(msr->info.msr_no, msr->info.reg.q);
63 * __save_processor_state() - Save CPU registers before creating a
64 * hibernation image and before restoring
65 * the memory state from it
66 * @ctxt: Structure to store the registers contents in.
68 * NOTE: If there is a CPU register the modification of which by the
69 * boot kernel (ie. the kernel used for loading the hibernation image)
70 * might affect the operations of the restored target kernel (ie. the one
71 * saved in the hibernation image), then its contents must be saved by this
72 * function. In other words, if kernel A is hibernated and different
73 * kernel B is used for loading the hibernation image into memory, the
74 * kernel A's __save_processor_state() function must save all registers
75 * needed by kernel A, so that it can operate correctly after the resume
76 * regardless of what kernel B does in the meantime.
78 static void __save_processor_state(struct saved_context *ctxt)
81 mtrr_save_fixed_ranges(NULL);
88 store_idt(&ctxt->idt);
91 * We save it here, but restore it only in the hibernate case.
92 * For ACPI S3 resume, this is loaded via 'early_gdt_desc' in 64-bit
93 * mode in "secondary_startup_64". In 32-bit mode it is done via
94 * 'pmode_gdt' in wakeup_start.
96 ctxt->gdt_desc.size = GDT_SIZE - 1;
97 ctxt->gdt_desc.address = (unsigned long)get_cpu_gdt_rw(smp_processor_id());
101 /* XMM0..XMM15 should be handled by kernel_fpu_begin(). */
105 savesegment(gs, ctxt->gs);
107 savesegment(fs, ctxt->fs);
108 savesegment(ds, ctxt->ds);
109 savesegment(es, ctxt->es);
111 rdmsrl(MSR_FS_BASE, ctxt->fs_base);
112 rdmsrl(MSR_GS_BASE, ctxt->kernelmode_gs_base);
113 rdmsrl(MSR_KERNEL_GS_BASE, ctxt->usermode_gs_base);
114 mtrr_save_fixed_ranges(NULL);
116 rdmsrl(MSR_EFER, ctxt->efer);
122 ctxt->cr0 = read_cr0();
123 ctxt->cr2 = read_cr2();
124 ctxt->cr3 = __read_cr3();
125 ctxt->cr4 = __read_cr4();
126 ctxt->misc_enable_saved = !rdmsrl_safe(MSR_IA32_MISC_ENABLE,
128 msr_save_context(ctxt);
131 /* Needed by apm.c */
132 void save_processor_state(void)
134 __save_processor_state(&saved_context);
135 x86_platform.save_sched_clock_state();
138 EXPORT_SYMBOL(save_processor_state);
141 static void do_fpu_end(void)
144 * Restore FPU regs if necessary.
149 static void fix_processor_context(void)
151 int cpu = smp_processor_id();
153 struct desc_struct *desc = get_cpu_gdt_rw(cpu);
158 * We need to reload TR, which requires that we change the
159 * GDT entry to indicate "available" first.
161 * XXX: This could probably all be replaced by a call to
164 set_tss_desc(cpu, &get_cpu_entry_area(cpu)->tss.x86_tss);
167 memcpy(&tss, &desc[GDT_ENTRY_TSS], sizeof(tss_desc));
168 tss.type = 0x9; /* The available 64-bit TSS (see AMD vol 2, pg 91 */
169 write_gdt_entry(desc, GDT_ENTRY_TSS, &tss, DESC_TSS);
171 syscall_init(); /* This sets MSR_*STAR and related */
173 if (boot_cpu_has(X86_FEATURE_SEP))
176 load_TR_desc(); /* This does ltr */
177 load_mm_ldt(current->active_mm); /* This does lldt */
178 initialize_tlbstate_and_flush();
182 /* The processor is back on the direct GDT, load back the fixmap */
183 load_fixmap_gdt(cpu);
187 * __restore_processor_state() - Restore the contents of CPU registers saved
188 * by __save_processor_state()
189 * @ctxt: Structure to load the registers contents from.
191 * The asm code that gets us here will have restored a usable GDT, although
192 * it will be pointing to the wrong alias.
194 static void notrace __restore_processor_state(struct saved_context *ctxt)
196 struct cpuinfo_x86 *c;
198 if (ctxt->misc_enable_saved)
199 wrmsrl(MSR_IA32_MISC_ENABLE, ctxt->misc_enable);
203 /* cr4 was introduced in the Pentium CPU */
206 __write_cr4(ctxt->cr4);
209 wrmsrl(MSR_EFER, ctxt->efer);
210 __write_cr4(ctxt->cr4);
212 write_cr3(ctxt->cr3);
213 write_cr2(ctxt->cr2);
214 write_cr0(ctxt->cr0);
216 /* Restore the IDT. */
217 load_idt(&ctxt->idt);
220 * Just in case the asm code got us here with the SS, DS, or ES
221 * out of sync with the GDT, update them.
223 loadsegment(ss, __KERNEL_DS);
224 loadsegment(ds, __USER_DS);
225 loadsegment(es, __USER_DS);
228 * Restore percpu access. Percpu access can happen in exception
229 * handlers or in complicated helpers like load_gs_index().
232 wrmsrl(MSR_GS_BASE, ctxt->kernelmode_gs_base);
234 loadsegment(fs, __KERNEL_PERCPU);
237 /* Restore the TSS, RO GDT, LDT, and usermode-relevant MSRs. */
238 fix_processor_context();
241 * Now that we have descriptor tables fully restored and working
242 * exception handling, restore the usermode segments.
245 loadsegment(ds, ctxt->es);
246 loadsegment(es, ctxt->es);
247 loadsegment(fs, ctxt->fs);
248 load_gs_index(ctxt->gs);
251 * Restore FSBASE and GSBASE after restoring the selectors, since
252 * restoring the selectors clobbers the bases. Keep in mind
253 * that MSR_KERNEL_GS_BASE is horribly misnamed.
255 wrmsrl(MSR_FS_BASE, ctxt->fs_base);
256 wrmsrl(MSR_KERNEL_GS_BASE, ctxt->usermode_gs_base);
258 loadsegment(gs, ctxt->gs);
262 tsc_verify_tsc_adjust(true);
263 x86_platform.restore_sched_clock_state();
265 perf_restore_debug_store();
267 c = &cpu_data(smp_processor_id());
268 if (cpu_has(c, X86_FEATURE_MSR_IA32_FEAT_CTL))
269 init_ia32_feat_ctl(c);
271 microcode_bsp_resume();
274 * This needs to happen after the microcode has been updated upon resume
275 * because some of the MSRs are "emulated" in microcode.
277 msr_restore_context(ctxt);
280 /* Needed by apm.c */
281 void notrace restore_processor_state(void)
283 __restore_processor_state(&saved_context);
286 EXPORT_SYMBOL(restore_processor_state);
289 #if defined(CONFIG_HIBERNATION) && defined(CONFIG_HOTPLUG_CPU)
290 static void resume_play_dead(void)
293 tboot_shutdown(TB_SHUTDOWN_WFS);
297 int hibernate_resume_nonboot_cpu_disable(void)
299 void (*play_dead)(void) = smp_ops.play_dead;
303 * Ensure that MONITOR/MWAIT will not be used in the "play dead" loop
304 * during hibernate image restoration, because it is likely that the
305 * monitored address will be actually written to at that time and then
306 * the "dead" CPU will attempt to execute instructions again, but the
307 * address in its instruction pointer may not be possible to resolve
308 * any more at that point (the page tables used by it previously may
309 * have been overwritten by hibernate image data).
311 * First, make sure that we wake up all the potentially disabled SMT
312 * threads which have been initially brought up and then put into
313 * mwait/cpuidle sleep.
314 * Those will be put to proper (not interfering with hibernation
315 * resume) sleep afterwards, and the resumed kernel will decide itself
316 * what to do with them.
318 ret = cpuhp_smt_enable();
321 smp_ops.play_dead = resume_play_dead;
322 ret = freeze_secondary_cpus(0);
323 smp_ops.play_dead = play_dead;
329 * When bsp_check() is called in hibernate and suspend, cpu hotplug
330 * is disabled already. So it's unnecessary to handle race condition between
331 * cpumask query and cpu hotplug.
333 static int bsp_check(void)
335 if (cpumask_first(cpu_online_mask) != 0) {
336 pr_warn("CPU0 is offline.\n");
343 static int bsp_pm_callback(struct notifier_block *nb, unsigned long action,
349 case PM_SUSPEND_PREPARE:
350 case PM_HIBERNATION_PREPARE:
353 #ifdef CONFIG_DEBUG_HOTPLUG_CPU0
354 case PM_RESTORE_PREPARE:
356 * When system resumes from hibernation, online CPU0 because
357 * 1. it's required for resume and
358 * 2. the CPU was online before hibernation
361 _debug_hotplug_cpu(0, 1);
363 case PM_POST_RESTORE:
365 * When a resume really happens, this code won't be called.
367 * This code is called only when user space hibernation software
368 * prepares for snapshot device during boot time. So we just
369 * call _debug_hotplug_cpu() to restore to CPU0's state prior to
370 * preparing the snapshot device.
372 * This works for normal boot case in our CPU0 hotplug debug
373 * mode, i.e. CPU0 is offline and user mode hibernation
374 * software initializes during boot time.
376 * If CPU0 is online and user application accesses snapshot
377 * device after boot time, this will offline CPU0 and user may
378 * see different CPU0 state before and after accessing
379 * the snapshot device. But hopefully this is not a case when
380 * user debugging CPU0 hotplug. Even if users hit this case,
381 * they can easily online CPU0 back.
383 * To simplify this debug code, we only consider normal boot
384 * case. Otherwise we need to remember CPU0's state and restore
385 * to that state and resolve racy conditions etc.
387 _debug_hotplug_cpu(0, 0);
393 return notifier_from_errno(ret);
396 static int __init bsp_pm_check_init(void)
399 * Set this bsp_pm_callback as lower priority than
400 * cpu_hotplug_pm_callback. So cpu_hotplug_pm_callback will be called
401 * earlier to disable cpu hotplug before bsp online check.
403 pm_notifier(bsp_pm_callback, -INT_MAX);
407 core_initcall(bsp_pm_check_init);
409 static int msr_build_context(const u32 *msr_id, const int num)
411 struct saved_msrs *saved_msrs = &saved_context.saved_msrs;
412 struct saved_msr *msr_array;
416 total_num = saved_msrs->num + num;
418 msr_array = kmalloc_array(total_num, sizeof(struct saved_msr), GFP_KERNEL);
420 pr_err("x86/pm: Can not allocate memory to save/restore MSRs during suspend.\n");
424 if (saved_msrs->array) {
426 * Multiple callbacks can invoke this function, so copy any
427 * MSR save requests from previous invocations.
429 memcpy(msr_array, saved_msrs->array,
430 sizeof(struct saved_msr) * saved_msrs->num);
432 kfree(saved_msrs->array);
435 for (i = saved_msrs->num, j = 0; i < total_num; i++, j++) {
438 msr_array[i].info.msr_no = msr_id[j];
439 msr_array[i].valid = !rdmsrl_safe(msr_id[j], &dummy);
440 msr_array[i].info.reg.q = 0;
442 saved_msrs->num = total_num;
443 saved_msrs->array = msr_array;
449 * The following sections are a quirk framework for problematic BIOSen:
450 * Sometimes MSRs are modified by the BIOSen after suspended to
451 * RAM, this might cause unexpected behavior after wakeup.
452 * Thus we save/restore these specified MSRs across suspend/resume
453 * in order to work around it.
455 * For any further problematic BIOSen/platforms,
456 * please add your own function similar to msr_initialize_bdw.
458 static int msr_initialize_bdw(const struct dmi_system_id *d)
460 /* Add any extra MSR ids into this array. */
461 u32 bdw_msr_id[] = { MSR_IA32_THERM_CONTROL };
463 pr_info("x86/pm: %s detected, MSR saving is needed during suspending.\n", d->ident);
464 return msr_build_context(bdw_msr_id, ARRAY_SIZE(bdw_msr_id));
467 static const struct dmi_system_id msr_save_dmi_table[] = {
469 .callback = msr_initialize_bdw,
470 .ident = "BROADWELL BDX_EP",
472 DMI_MATCH(DMI_PRODUCT_NAME, "GRANTLEY"),
473 DMI_MATCH(DMI_PRODUCT_VERSION, "E63448-400"),
479 static int msr_save_cpuid_features(const struct x86_cpu_id *c)
481 u32 cpuid_msr_id[] = {
482 MSR_AMD64_CPUID_FN_1,
485 pr_info("x86/pm: family %#hx cpu detected, MSR saving is needed during suspending.\n",
488 return msr_build_context(cpuid_msr_id, ARRAY_SIZE(cpuid_msr_id));
491 static const struct x86_cpu_id msr_save_cpu_table[] = {
492 X86_MATCH_VENDOR_FAM(AMD, 0x15, &msr_save_cpuid_features),
493 X86_MATCH_VENDOR_FAM(AMD, 0x16, &msr_save_cpuid_features),
497 typedef int (*pm_cpu_match_t)(const struct x86_cpu_id *);
498 static int pm_cpu_check(const struct x86_cpu_id *c)
500 const struct x86_cpu_id *m;
503 m = x86_match_cpu(msr_save_cpu_table);
507 fn = (pm_cpu_match_t)m->driver_data;
514 static void pm_save_spec_msr(void)
516 struct msr_enumeration {
520 { MSR_IA32_SPEC_CTRL, X86_FEATURE_MSR_SPEC_CTRL },
521 { MSR_IA32_TSX_CTRL, X86_FEATURE_MSR_TSX_CTRL },
522 { MSR_TSX_FORCE_ABORT, X86_FEATURE_TSX_FORCE_ABORT },
523 { MSR_IA32_MCU_OPT_CTRL, X86_FEATURE_SRBDS_CTRL },
524 { MSR_AMD64_LS_CFG, X86_FEATURE_LS_CFG_SSBD },
525 { MSR_AMD64_DE_CFG, X86_FEATURE_LFENCE_RDTSC },
529 for (i = 0; i < ARRAY_SIZE(msr_enum); i++) {
530 if (boot_cpu_has(msr_enum[i].feature))
531 msr_build_context(&msr_enum[i].msr_no, 1);
535 static int pm_check_save_msr(void)
537 dmi_check_system(msr_save_dmi_table);
538 pm_cpu_check(msr_save_cpu_table);
544 device_initcall(pm_check_save_msr);