1 // SPDX-License-Identifier: GPL-2.0-only
3 * Suspend support specific for i386/x86-64.
5 * Copyright (c) 2007 Rafael J. Wysocki <rjw@sisk.pl>
6 * Copyright (c) 2002 Pavel Machek <pavel@ucw.cz>
7 * Copyright (c) 2001 Patrick Mochel <mochel@osdl.org>
10 #include <linux/suspend.h>
11 #include <linux/export.h>
12 #include <linux/smp.h>
13 #include <linux/perf_event.h>
14 #include <linux/tboot.h>
15 #include <linux/dmi.h>
17 #include <asm/pgtable.h>
18 #include <asm/proto.h>
22 #include <asm/suspend.h>
23 #include <asm/fpu/internal.h>
24 #include <asm/debugreg.h>
26 #include <asm/mmu_context.h>
27 #include <asm/cpu_device_id.h>
28 #include <asm/microcode.h>
31 __visible unsigned long saved_context_ebx;
32 __visible unsigned long saved_context_esp, saved_context_ebp;
33 __visible unsigned long saved_context_esi, saved_context_edi;
34 __visible unsigned long saved_context_eflags;
36 struct saved_context saved_context;
38 static void msr_save_context(struct saved_context *ctxt)
40 struct saved_msr *msr = ctxt->saved_msrs.array;
41 struct saved_msr *end = msr + ctxt->saved_msrs.num;
45 rdmsrl(msr->info.msr_no, msr->info.reg.q);
50 static void msr_restore_context(struct saved_context *ctxt)
52 struct saved_msr *msr = ctxt->saved_msrs.array;
53 struct saved_msr *end = msr + ctxt->saved_msrs.num;
57 wrmsrl(msr->info.msr_no, msr->info.reg.q);
63 * __save_processor_state - save CPU registers before creating a
64 * hibernation image and before restoring the memory state from it
65 * @ctxt - structure to store the registers contents in
67 * NOTE: If there is a CPU register the modification of which by the
68 * boot kernel (ie. the kernel used for loading the hibernation image)
69 * might affect the operations of the restored target kernel (ie. the one
70 * saved in the hibernation image), then its contents must be saved by this
71 * function. In other words, if kernel A is hibernated and different
72 * kernel B is used for loading the hibernation image into memory, the
73 * kernel A's __save_processor_state() function must save all registers
74 * needed by kernel A, so that it can operate correctly after the resume
75 * regardless of what kernel B does in the meantime.
77 static void __save_processor_state(struct saved_context *ctxt)
80 mtrr_save_fixed_ranges(NULL);
87 store_idt(&ctxt->idt);
90 * We save it here, but restore it only in the hibernate case.
91 * For ACPI S3 resume, this is loaded via 'early_gdt_desc' in 64-bit
92 * mode in "secondary_startup_64". In 32-bit mode it is done via
93 * 'pmode_gdt' in wakeup_start.
95 ctxt->gdt_desc.size = GDT_SIZE - 1;
96 ctxt->gdt_desc.address = (unsigned long)get_cpu_gdt_rw(smp_processor_id());
100 /* XMM0..XMM15 should be handled by kernel_fpu_begin(). */
104 #ifdef CONFIG_X86_32_LAZY_GS
105 savesegment(gs, ctxt->gs);
108 savesegment(gs, ctxt->gs);
109 savesegment(fs, ctxt->fs);
110 savesegment(ds, ctxt->ds);
111 savesegment(es, ctxt->es);
113 rdmsrl(MSR_FS_BASE, ctxt->fs_base);
114 rdmsrl(MSR_GS_BASE, ctxt->kernelmode_gs_base);
115 rdmsrl(MSR_KERNEL_GS_BASE, ctxt->usermode_gs_base);
116 mtrr_save_fixed_ranges(NULL);
118 rdmsrl(MSR_EFER, ctxt->efer);
124 ctxt->cr0 = read_cr0();
125 ctxt->cr2 = read_cr2();
126 ctxt->cr3 = __read_cr3();
127 ctxt->cr4 = __read_cr4();
128 ctxt->misc_enable_saved = !rdmsrl_safe(MSR_IA32_MISC_ENABLE,
130 msr_save_context(ctxt);
133 /* Needed by apm.c */
134 void save_processor_state(void)
136 __save_processor_state(&saved_context);
137 x86_platform.save_sched_clock_state();
140 EXPORT_SYMBOL(save_processor_state);
143 static void do_fpu_end(void)
146 * Restore FPU regs if necessary.
151 static void fix_processor_context(void)
153 int cpu = smp_processor_id();
155 struct desc_struct *desc = get_cpu_gdt_rw(cpu);
160 * We need to reload TR, which requires that we change the
161 * GDT entry to indicate "available" first.
163 * XXX: This could probably all be replaced by a call to
166 set_tss_desc(cpu, &get_cpu_entry_area(cpu)->tss.x86_tss);
169 memcpy(&tss, &desc[GDT_ENTRY_TSS], sizeof(tss_desc));
170 tss.type = 0x9; /* The available 64-bit TSS (see AMD vol 2, pg 91 */
171 write_gdt_entry(desc, GDT_ENTRY_TSS, &tss, DESC_TSS);
173 syscall_init(); /* This sets MSR_*STAR and related */
175 if (boot_cpu_has(X86_FEATURE_SEP))
178 load_TR_desc(); /* This does ltr */
179 load_mm_ldt(current->active_mm); /* This does lldt */
180 initialize_tlbstate_and_flush();
184 /* The processor is back on the direct GDT, load back the fixmap */
185 load_fixmap_gdt(cpu);
189 * __restore_processor_state - restore the contents of CPU registers saved
190 * by __save_processor_state()
191 * @ctxt - structure to load the registers contents from
193 * The asm code that gets us here will have restored a usable GDT, although
194 * it will be pointing to the wrong alias.
196 static void notrace __restore_processor_state(struct saved_context *ctxt)
198 if (ctxt->misc_enable_saved)
199 wrmsrl(MSR_IA32_MISC_ENABLE, ctxt->misc_enable);
203 /* cr4 was introduced in the Pentium CPU */
206 __write_cr4(ctxt->cr4);
209 wrmsrl(MSR_EFER, ctxt->efer);
210 __write_cr4(ctxt->cr4);
212 write_cr3(ctxt->cr3);
213 write_cr2(ctxt->cr2);
214 write_cr0(ctxt->cr0);
216 /* Restore the IDT. */
217 load_idt(&ctxt->idt);
220 * Just in case the asm code got us here with the SS, DS, or ES
221 * out of sync with the GDT, update them.
223 loadsegment(ss, __KERNEL_DS);
224 loadsegment(ds, __USER_DS);
225 loadsegment(es, __USER_DS);
228 * Restore percpu access. Percpu access can happen in exception
229 * handlers or in complicated helpers like load_gs_index().
232 wrmsrl(MSR_GS_BASE, ctxt->kernelmode_gs_base);
234 loadsegment(fs, __KERNEL_PERCPU);
235 loadsegment(gs, __KERNEL_STACK_CANARY);
238 /* Restore the TSS, RO GDT, LDT, and usermode-relevant MSRs. */
239 fix_processor_context();
242 * Now that we have descriptor tables fully restored and working
243 * exception handling, restore the usermode segments.
246 loadsegment(ds, ctxt->es);
247 loadsegment(es, ctxt->es);
248 loadsegment(fs, ctxt->fs);
249 load_gs_index(ctxt->gs);
252 * Restore FSBASE and GSBASE after restoring the selectors, since
253 * restoring the selectors clobbers the bases. Keep in mind
254 * that MSR_KERNEL_GS_BASE is horribly misnamed.
256 wrmsrl(MSR_FS_BASE, ctxt->fs_base);
257 wrmsrl(MSR_KERNEL_GS_BASE, ctxt->usermode_gs_base);
258 #elif defined(CONFIG_X86_32_LAZY_GS)
259 loadsegment(gs, ctxt->gs);
263 tsc_verify_tsc_adjust(true);
264 x86_platform.restore_sched_clock_state();
266 perf_restore_debug_store();
268 microcode_bsp_resume();
271 * This needs to happen after the microcode has been updated upon resume
272 * because some of the MSRs are "emulated" in microcode.
274 msr_restore_context(ctxt);
277 /* Needed by apm.c */
278 void notrace restore_processor_state(void)
280 __restore_processor_state(&saved_context);
283 EXPORT_SYMBOL(restore_processor_state);
286 #if defined(CONFIG_HIBERNATION) && defined(CONFIG_HOTPLUG_CPU)
287 static void resume_play_dead(void)
290 tboot_shutdown(TB_SHUTDOWN_WFS);
294 int hibernate_resume_nonboot_cpu_disable(void)
296 void (*play_dead)(void) = smp_ops.play_dead;
300 * Ensure that MONITOR/MWAIT will not be used in the "play dead" loop
301 * during hibernate image restoration, because it is likely that the
302 * monitored address will be actually written to at that time and then
303 * the "dead" CPU will attempt to execute instructions again, but the
304 * address in its instruction pointer may not be possible to resolve
305 * any more at that point (the page tables used by it previously may
306 * have been overwritten by hibernate image data).
308 * First, make sure that we wake up all the potentially disabled SMT
309 * threads which have been initially brought up and then put into
310 * mwait/cpuidle sleep.
311 * Those will be put to proper (not interfering with hibernation
312 * resume) sleep afterwards, and the resumed kernel will decide itself
313 * what to do with them.
315 ret = cpuhp_smt_enable();
318 smp_ops.play_dead = resume_play_dead;
319 ret = disable_nonboot_cpus();
320 smp_ops.play_dead = play_dead;
326 * When bsp_check() is called in hibernate and suspend, cpu hotplug
327 * is disabled already. So it's unnessary to handle race condition between
328 * cpumask query and cpu hotplug.
330 static int bsp_check(void)
332 if (cpumask_first(cpu_online_mask) != 0) {
333 pr_warn("CPU0 is offline.\n");
340 static int bsp_pm_callback(struct notifier_block *nb, unsigned long action,
346 case PM_SUSPEND_PREPARE:
347 case PM_HIBERNATION_PREPARE:
350 #ifdef CONFIG_DEBUG_HOTPLUG_CPU0
351 case PM_RESTORE_PREPARE:
353 * When system resumes from hibernation, online CPU0 because
354 * 1. it's required for resume and
355 * 2. the CPU was online before hibernation
358 _debug_hotplug_cpu(0, 1);
360 case PM_POST_RESTORE:
362 * When a resume really happens, this code won't be called.
364 * This code is called only when user space hibernation software
365 * prepares for snapshot device during boot time. So we just
366 * call _debug_hotplug_cpu() to restore to CPU0's state prior to
367 * preparing the snapshot device.
369 * This works for normal boot case in our CPU0 hotplug debug
370 * mode, i.e. CPU0 is offline and user mode hibernation
371 * software initializes during boot time.
373 * If CPU0 is online and user application accesses snapshot
374 * device after boot time, this will offline CPU0 and user may
375 * see different CPU0 state before and after accessing
376 * the snapshot device. But hopefully this is not a case when
377 * user debugging CPU0 hotplug. Even if users hit this case,
378 * they can easily online CPU0 back.
380 * To simplify this debug code, we only consider normal boot
381 * case. Otherwise we need to remember CPU0's state and restore
382 * to that state and resolve racy conditions etc.
384 _debug_hotplug_cpu(0, 0);
390 return notifier_from_errno(ret);
393 static int __init bsp_pm_check_init(void)
396 * Set this bsp_pm_callback as lower priority than
397 * cpu_hotplug_pm_callback. So cpu_hotplug_pm_callback will be called
398 * earlier to disable cpu hotplug before bsp online check.
400 pm_notifier(bsp_pm_callback, -INT_MAX);
404 core_initcall(bsp_pm_check_init);
406 static int msr_build_context(const u32 *msr_id, const int num)
408 struct saved_msrs *saved_msrs = &saved_context.saved_msrs;
409 struct saved_msr *msr_array;
413 total_num = saved_msrs->num + num;
415 msr_array = kmalloc_array(total_num, sizeof(struct saved_msr), GFP_KERNEL);
417 pr_err("x86/pm: Can not allocate memory to save/restore MSRs during suspend.\n");
421 if (saved_msrs->array) {
423 * Multiple callbacks can invoke this function, so copy any
424 * MSR save requests from previous invocations.
426 memcpy(msr_array, saved_msrs->array,
427 sizeof(struct saved_msr) * saved_msrs->num);
429 kfree(saved_msrs->array);
432 for (i = saved_msrs->num, j = 0; i < total_num; i++, j++) {
435 msr_array[i].info.msr_no = msr_id[j];
436 msr_array[i].valid = !rdmsrl_safe(msr_id[j], &dummy);
437 msr_array[i].info.reg.q = 0;
439 saved_msrs->num = total_num;
440 saved_msrs->array = msr_array;
446 * The following sections are a quirk framework for problematic BIOSen:
447 * Sometimes MSRs are modified by the BIOSen after suspended to
448 * RAM, this might cause unexpected behavior after wakeup.
449 * Thus we save/restore these specified MSRs across suspend/resume
450 * in order to work around it.
452 * For any further problematic BIOSen/platforms,
453 * please add your own function similar to msr_initialize_bdw.
455 static int msr_initialize_bdw(const struct dmi_system_id *d)
457 /* Add any extra MSR ids into this array. */
458 u32 bdw_msr_id[] = { MSR_IA32_THERM_CONTROL };
460 pr_info("x86/pm: %s detected, MSR saving is needed during suspending.\n", d->ident);
461 return msr_build_context(bdw_msr_id, ARRAY_SIZE(bdw_msr_id));
464 static const struct dmi_system_id msr_save_dmi_table[] = {
466 .callback = msr_initialize_bdw,
467 .ident = "BROADWELL BDX_EP",
469 DMI_MATCH(DMI_PRODUCT_NAME, "GRANTLEY"),
470 DMI_MATCH(DMI_PRODUCT_VERSION, "E63448-400"),
476 static int msr_save_cpuid_features(const struct x86_cpu_id *c)
478 u32 cpuid_msr_id[] = {
479 MSR_AMD64_CPUID_FN_1,
482 pr_info("x86/pm: family %#hx cpu detected, MSR saving is needed during suspending.\n",
485 return msr_build_context(cpuid_msr_id, ARRAY_SIZE(cpuid_msr_id));
488 static const struct x86_cpu_id msr_save_cpu_table[] = {
490 .vendor = X86_VENDOR_AMD,
492 .model = X86_MODEL_ANY,
493 .feature = X86_FEATURE_ANY,
494 .driver_data = (kernel_ulong_t)msr_save_cpuid_features,
497 .vendor = X86_VENDOR_AMD,
499 .model = X86_MODEL_ANY,
500 .feature = X86_FEATURE_ANY,
501 .driver_data = (kernel_ulong_t)msr_save_cpuid_features,
506 typedef int (*pm_cpu_match_t)(const struct x86_cpu_id *);
507 static int pm_cpu_check(const struct x86_cpu_id *c)
509 const struct x86_cpu_id *m;
512 m = x86_match_cpu(msr_save_cpu_table);
516 fn = (pm_cpu_match_t)m->driver_data;
523 static void pm_save_spec_msr(void)
525 struct msr_enumeration {
529 { MSR_IA32_SPEC_CTRL, X86_FEATURE_MSR_SPEC_CTRL },
530 { MSR_IA32_TSX_CTRL, X86_FEATURE_MSR_TSX_CTRL },
531 { MSR_TSX_FORCE_ABORT, X86_FEATURE_TSX_FORCE_ABORT },
532 { MSR_IA32_MCU_OPT_CTRL, X86_FEATURE_SRBDS_CTRL },
533 { MSR_AMD64_LS_CFG, X86_FEATURE_LS_CFG_SSBD },
534 { MSR_AMD64_DE_CFG, X86_FEATURE_LFENCE_RDTSC },
538 for (i = 0; i < ARRAY_SIZE(msr_enum); i++) {
539 if (boot_cpu_has(msr_enum[i].feature))
540 msr_build_context(&msr_enum[i].msr_no, 1);
544 static int pm_check_save_msr(void)
546 dmi_check_system(msr_save_dmi_table);
547 pm_cpu_check(msr_save_cpu_table);
553 device_initcall(pm_check_save_msr);